2376 lines
65 KiB
Plaintext
2376 lines
65 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/th1520-fm-ap-clock.h>
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#include <dt-bindings/clock/th1520-vpsys.h>
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#include <dt-bindings/clock/th1520-vosys.h>
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#include <dt-bindings/clock/th1520-visys.h>
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#include <dt-bindings/clock/th1520-dspsys.h>
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#include <dt-bindings/clock/th1520-audiosys.h>
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#include <dt-bindings/clock/th1520-miscsys.h>
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#include <dt-bindings/reset/thead,th1520-reset.h>
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#include <dt-bindings/firmware/thead/rsrc.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/soc/xuantie,th1520-iopmp.h>
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/ {
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compatible = "thead,th1520";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &audio_i2c0;
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i2c6 = &audio_i2c1;
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mmc0 = &emmc;
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mmc1 = &sdio0;
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mmc2 = &sdio1;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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spi0 = &spi;
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spi1 = &qspi0;
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spi2 = &qspi1;
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ap_i2s = &ap_i2s;
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i2s0 = &i2s0;
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i2s1 = &i2s1;
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i2s2 = &i2s2;
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};
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system_monitor: system-monitor {
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compatible = "th1520,system-monitor";
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <3000000>;
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c910_0: cpu@0 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc_xtheadvector";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicntr", "zicsr",
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"zifencei", "zihpm", "xtheadvector", "xtheadsscofpmf";
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reg = <0>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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video-4k-minfreq = <1848000000>;
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qos-mid-minfreq = <750000000>;
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#cooling-cells = <2>;
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dynamic-power-coefficient = <500>;
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clock-latency = <61036>;
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clocks = <&clk C910_CCLK>,
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<&clk C910_CCLK_I0>,
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<&clk CPU_PLL1_FOUTPOSTDIV>,
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<&clk CPU_PLL0_FOUTPOSTDIV>;
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clock-names = "c910_cclk", "c910_cclk_i0",
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"cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_1: cpu@1 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc_xtheadvector";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicntr", "zicsr",
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"zifencei", "zihpm", "xtheadvector", "xtheadsscofpmf";
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reg = <1>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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#cooling-cells = <2>;
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dynamic-power-coefficient = <500>;
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clock-latency = <61036>;
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clocks = <&clk C910_CCLK>,
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<&clk C910_CCLK_I0>,
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<&clk CPU_PLL1_FOUTPOSTDIV>,
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<&clk CPU_PLL0_FOUTPOSTDIV>;
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clock-names = "c910_cclk", "c910_cclk_i0",
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"cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_2: cpu@2 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc_xtheadvector";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicntr", "zicsr",
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"zifencei", "zihpm", "xtheadvector", "xtheadsscofpmf";
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reg = <2>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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#cooling-cells = <2>;
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dynamic-power-coefficient = <500>;
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clock-latency = <61036>;
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clocks = <&clk C910_CCLK>,
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<&clk C910_CCLK_I0>,
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<&clk CPU_PLL1_FOUTPOSTDIV>,
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<&clk CPU_PLL0_FOUTPOSTDIV>;
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clock-names = "c910_cclk", "c910_cclk_i0",
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"cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_3: cpu@3 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc_xtheadvector";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicntr", "zicsr",
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"zifencei", "zihpm", "xtheadvector", "xtheadsscofpmf";
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reg = <3>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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#cooling-cells = <2>;
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dynamic-power-coefficient = <500>;
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clock-latency = <61036>;
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clocks = <&clk C910_CCLK>,
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<&clk C910_CCLK_I0>,
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<&clk CPU_PLL1_FOUTPOSTDIV>,
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<&clk CPU_PLL0_FOUTPOSTDIV>;
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clock-names = "c910_cclk", "c910_cclk_i0",
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"cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <1048576>;
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cache-sets = <1024>;
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cache-unified;
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};
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};
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resmem: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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};
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pmu {
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compatible = "riscv,pmu";
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riscv,event-to-mhpmevent =
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/* PMU_HW_CACHE_REFERENCES:3 */
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/* PMU_HW_CACHE_MISSES:4 */
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/* PMU_HW_BRANCH_INSTRUCTIONS:5 */
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<0x00005 0x00000000 0x00000007>,
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/* PMU_HW_BRANCH_MISSES:6 */
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<0x00006 0x00000000 0x00000006>,
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/* PMU_HW_BUS_CYCLES:7 */
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/* PMU_HW_STALLED_CYCLES_FRONTEND:8 */
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<0x00008 0x00000000 0x00000027>,
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/* PMU_HW_STALLED_CYCLES_BACKEND:9 */
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<0x00009 0x00000000 0x00000028>,
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/* PMU_HW_REF_CPU_CYCLES:10 */
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/* L1D_READ_ACCESS:0x10000 */
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<0x10000 0x00000000 0x0000000c>,
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/* L1D_READ_MISS:0x10001 */
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<0x10001 0x00000000 0x0000000d>,
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/* L1D_WRITE_ACCESS:0x10002 */
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<0x10002 0x00000000 0x0000000e>,
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/* L1D_WRITE_MISS:0x10003 */
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<0x10003 0x00000000 0x0000000f>,
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/* L1I_READ_ACCESS:0x10008 */
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<0x10008 0x00000000 0x00000001>,
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/* L1I_READ_MISS:0x10009 */
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<0x10009 0x00000000 0x00000002>,
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/* dTLB read miss :0x10019 */
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<0x10019 0x00000000 0x00000004>,
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/* iTLB read miss :0x10021 */
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<0x10021 0x00000000 0x00000003>;
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/* LL_READ_ACCESS:0x10010 */
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/* LL_READ_MISS:0x10011 */
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/* LL_WRITE_ACCESS:0x10012 */
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/* LL_WRITE_MISS:0x10013 */
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/* BPU_READ_ACCESS:0x10028 */
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/* BPU_READ_MISS:0x10029 */
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riscv,event-to-mhpmcounters =
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/* The Xuantie processor only implements 31 mhpmcounters, so the bitmap is 0xfffffff8 */
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<0x00005 0x00005 0x0007fff8>,
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<0x00006 0x00006 0x0007fff8>,
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<0x00008 0x00008 0x0007fff8>,
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<0x00009 0x00009 0x0007fff8>,
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<0x10000 0x10000 0x0007fff8>,
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<0x10001 0x10001 0x0007fff8>,
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<0x10002 0x10002 0x0007fff8>,
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<0x10003 0x10003 0x0007fff8>,
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<0x10008 0x10008 0x0007fff8>,
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<0x10009 0x10009 0x0007fff8>,
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<0x10019 0x10019 0x0007fff8>,
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<0x10021 0x10021 0x0007fff8>;
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riscv,raw-event-to-mhpmcounters =
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<0x00 0x00 0xffffffff 0xffffff00 0x0007fff8>;
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};
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_24m";
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#clock-cells = <0>;
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};
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osc_32k: 32k-oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_32k";
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#clock-cells = <0>;
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};
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rc_24m: clock-rc-24m {
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compatible = "fixed-clock";
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clock-output-names = "rc_24m";
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#clock-cells = <0>;
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};
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aonsys_clk: aonsys-clk {
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compatible = "fixed-clock";
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clock-output-names = "aonsys_clk";
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#clock-cells = <0>;
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};
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audiosys_clk: audiosys-clk {
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compatible = "fixed-clock";
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clock-output-names = "audiosys_clk";
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#clock-cells = <0>;
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};
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apb_clk: apb-clk-clock {
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compatible = "fixed-clock";
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clock-output-names = "apb_clk";
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#clock-cells = <0>;
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};
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uart_sclk: uart-sclk-clock {
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compatible = "fixed-clock";
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clock-output-names = "uart_sclk";
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#clock-cells = <0>;
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};
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sdhci_clk: sdhci-clock {
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compatible = "fixed-clock";
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clock-frequency = <198000000>;
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clock-output-names = "sdhci_clk";
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#clock-cells = <0>;
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};
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gmac_axi_clk: gmac-axi-clock {
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compatible = "fixed-clock";
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clock-output-names = "gmac_axi_clk";
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#clock-cells = <0>;
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};
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gmac_clk: gmac-clock {
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compatible = "fixed-clock";
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clock-output-names = "gmac_clk";
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#clock-cells = <0>;
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};
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stmmac_axi_config: stmmac-axi-config {
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snps,wr_osr_lmt = <15>;
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snps,rd_osr_lmt = <15>;
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snps,blen = <0 0 64 32 0 0 0>;
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};
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aon: aon_subsys {
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compatible = "thead,th1520-aon";
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mbox-names = "aon";
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mboxes = <&mbox_910t 1 0>;
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opensbi-mboxes = <&mbox_910r>;
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status = "okay";
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pd: th1520-aon-pd {
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compatible = "thead,th1520-aon-pd";
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#power-domain-cells = <1>;
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};
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cpufreq: c910_cpufreq {
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compatible = "xuantie,th1520-cpufreq";
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status = "okay";
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};
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};
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aon_iram: aon-iram@ffffef8000 {
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compatible = "syscon";
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reg = <0xff 0xffef8000 0x0 0x10000>;
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&pvt 0>;
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trips {
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cpu_threshold: trip0 {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_target: trip1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: trip2 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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cpu_cdev {
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trip = <&cpu_target>;
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cooling-device =
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<&c910_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&c910_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&c910_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&c910_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <1024>;
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};
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};
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};
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dev-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&pvt 1>;
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trips {
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dev_threshold: trip0 {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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dev_target: trip1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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dev_crit: trip2 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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npu_devfreq {
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trip = <&dev_target>;
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cooling-device =
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<&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <1024>;
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};
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dsp0_devfreq {
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trip = <&dev_target>;
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cooling-device =
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<&xtensa_dsp0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <1024>;
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};
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dsp1_devfreq {
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trip = <&dev_target>;
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cooling-device =
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<&xtensa_dsp1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <1024>;
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};
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};
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};
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};
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display-subsystem {
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compatible = "verisilicon,display-subsystem";
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ports = <&dpu_disp0>, <&dpu_disp1>;
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status = "okay";
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};
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dpu-encoders {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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dpu_enc0: dpu-encoder@0 {
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/* default encoder is DSI */
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compatible = "verisilicon,dsi-encoder";
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reg = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* input */
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port@0 {
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reg = <0>;
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enc0_in: endpoint {
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remote-endpoint = <&disp0_out>;
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};
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};
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};
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};
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dpu_enc1: dpu-encoder@1 {
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/* default encoder is DSI */
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compatible = "verisilicon,dsi-encoder";
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reg = <1>;
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|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/* input */
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
enc1_in: endpoint {
|
|
remote-endpoint = <&disp1_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&plic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-noncoherent;
|
|
ranges;
|
|
|
|
audio_i2c0: i2c@ffcb01a000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xff 0xcb01a000 0x0 0x1000>;
|
|
clocks = <&apb_clk>;
|
|
interrupts = <182 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <100000>;
|
|
dma-mode;
|
|
dmas = <&dmac2 21>, <&dmac2 20>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
ss_hcnt = /bits/ 16 <0x82>;
|
|
ss_lcnt = /bits/ 16 <0x78>;
|
|
fs_hcnt = /bits/ 16 <0x37>;
|
|
fs_lcnt = /bits/ 16 <0x42>;
|
|
fp_hcnt = /bits/ 16 <0x14>;
|
|
fp_lcnt = /bits/ 16 <0x1a>;
|
|
hs_hcnt = /bits/ 16 <0x5>;
|
|
hs_lcnt = /bits/ 16 <0x15>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
audio_i2c1: i2c@ffcb01b000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xff 0xcb01b000 0x0 0x1000>;
|
|
clocks = <&apb_clk>;
|
|
interrupts = <183 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <100000>;
|
|
dma-mode;
|
|
dmas = <&dmac2 23>, <&dmac2 22>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
ss_hcnt = /bits/ 16 <0x82>;
|
|
ss_lcnt = /bits/ 16 <0x78>;
|
|
fs_hcnt = /bits/ 16 <0x37>;
|
|
fs_lcnt = /bits/ 16 <0x42>;
|
|
fp_hcnt = /bits/ 16 <0x14>;
|
|
fp_lcnt = /bits/ 16 <0x1a>;
|
|
hs_hcnt = /bits/ 16 <0x5>;
|
|
hs_lcnt = /bits/ 16 <0x15>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
ap_i2s: ap-i2s@ffe7034000 {
|
|
#sound-dai-cells = <1>;
|
|
compatible = "xuantie,th1520-i2s";
|
|
reg = <0xff 0xe7034000 0x0 0x4000>;
|
|
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac0 35>, <&dmac0 40>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&vosys_clk_gate TH1520_CLKGEN_HDMI_I2S_CLK>;
|
|
clock-names = "pclk";
|
|
resets = <&rst TH1520_RESET_HDMI_I2S>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s0: audio-i2s0@ffcb014000 {
|
|
#sound-dai-cells = <1>;
|
|
compatible = "xuantie,th1520-i2s";
|
|
reg = <0xff 0xcb014000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
interrupts = <174 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 9>, <&dmac2 8>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_I2S0>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_I2S0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1: audio-i2s1@ffcb015000 {
|
|
#sound-dai-cells = <1>;
|
|
compatible = "xuantie,th1520-i2s";
|
|
reg = <0xff 0xcb015000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
interrupts = <175 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 11>, <&dmac2 10>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_I2S1>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_I2S1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s2: audio-i2s2@ffcb016000 {
|
|
#sound-dai-cells = <1>;
|
|
compatible = "xuantie,th1520-i2s";
|
|
reg = <0xff 0xcb016000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
interrupts = <176 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 13>, <&dmac2 12>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_I2S2>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_I2S2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_8ch_sd0: i2s-8ch-sd0@ffcb017000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-i2s-8ch";
|
|
reg = <0xff 0xcb017000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
interrupts = <177 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 36>, <&dmac2 14>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_I2S8CH>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_I2S8CH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_8ch_sd1: i2s-8ch-sd1@ffcb017000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-i2s-8ch";
|
|
reg = <0xff 0xcb017000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
interrupts = <177 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 37>, <&dmac2 15>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_I2S8CH>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_I2S8CH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_8ch_sd2: i2s-8ch-sd2@ffcb017000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-i2s-8ch";
|
|
reg = <0xff 0xcb017000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
interrupts = <177 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 38>, <&dmac2 16>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_I2S8CH>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_I2S8CH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_8ch_sd3: i2s-8ch-sd3@ffcb017000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-i2s-8ch";
|
|
reg = <0xff 0xcb017000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
interrupts = <177 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 39>, <&dmac2 17>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_I2S8CH>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_I2S8CH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm_slot1: tdm1@ffcb012000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-tdm";
|
|
reg = <0xff 0xcb012000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,tdm_slots = <8>;
|
|
th1520,tdm_slot_num = <1>;
|
|
interrupts = <178 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 28>;
|
|
dma-names = "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_TDM>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_TDM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm_slot2: tdm2@ffcb012000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-tdm";
|
|
reg = <0xff 0xcb012000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,tdm_slots = <8>;
|
|
th1520,tdm_slot_num = <2>;
|
|
interrupts = <178 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 29>;
|
|
dma-names = "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_TDM>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_TDM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm_slot3: tdm3@ffcb012000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-tdm";
|
|
reg = <0xff 0xcb012000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,tdm_slots = <8>;
|
|
th1520,tdm_slot_num = <3>;
|
|
interrupts = <178 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 30>;
|
|
dma-names = "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_TDM>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_TDM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm_slot4: tdm4@ffcb012000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-tdm";
|
|
reg = <0xff 0xcb012000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,tdm_slots = <8>;
|
|
th1520,tdm_slot_num = <4>;
|
|
interrupts = <178 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 31>;
|
|
dma-names = "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_TDM>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_TDM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm_slot5: tdm5@ffcb012000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-tdm";
|
|
reg = <0xff 0xcb012000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,tdm_slots = <8>;
|
|
th1520,tdm_slot_num = <5>;
|
|
interrupts = <178 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 32>;
|
|
dma-names = "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_TDM>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_TDM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm_slot6: tdm6@ffcb012000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-tdm";
|
|
reg = <0xff 0xcb012000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,tdm_slots = <8>;
|
|
th1520,tdm_slot_num = <6>;
|
|
interrupts = <178 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 33>;
|
|
dma-names = "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_TDM>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_TDM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm_slot7: tdm7@ffcb012000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-tdm";
|
|
reg = <0xff 0xcb012000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,tdm_slots = <8>;
|
|
th1520,tdm_slot_num = <7>;
|
|
interrupts = <178 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 34>;
|
|
dma-names = "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_TDM>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_TDM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm_slot8: tdm8@ffcb012000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-tdm";
|
|
reg = <0xff 0xcb012000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,tdm_slots = <8>;
|
|
th1520,tdm_slot_num = <8>;
|
|
interrupts = <178 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 35>;
|
|
dma-names = "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_TDM>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_TDM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif0: spdif@ffcb018000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-spdif";
|
|
reg = <0xff 0xcb018000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,spdif_idx = <0>;
|
|
interrupts = <179 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 25>, <&dmac2 24>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_SPDIF0>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_SPDIF0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif1: spdif@ffcb019000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "xuantie,th1520-spdif";
|
|
reg = <0xff 0xcb019000 0x0 0x1000>;
|
|
audio-cpr-regmap = <&audio_cpr>;
|
|
pinctrl-names = "default";
|
|
th1520,spdif_idx = <1>;
|
|
interrupts = <180 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac2 27>, <&dmac2 26>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
clocks = <&audiosys_clk_gate TH1520_CLKGEN_AUDIO_SPDIF1>;
|
|
clock-names = "pclk";
|
|
resets = <&audiosys_rst TH1520_RESET_AUD_SPDIF1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
reset: reset-sample {
|
|
compatible = "thead,reset-sample";
|
|
plic-delegate = <0xff 0xd81ffffc>;
|
|
entry-reg = <0xff 0xff019050>;
|
|
entry-cnt = <4>;
|
|
control-reg = <0xff 0xff015004>;
|
|
control-val = <0x1f>;
|
|
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
|
|
};
|
|
|
|
plic: interrupt-controller@ffd8000000 {
|
|
compatible = "thead,th1520-plic", "thead,c900-plic", "riscv,plic0";
|
|
reg = <0xff 0xd8000000 0x0 0x01000000>;
|
|
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
|
|
<&cpu1_intc 11>, <&cpu1_intc 9>,
|
|
<&cpu2_intc 11>, <&cpu2_intc 9>,
|
|
<&cpu3_intc 11>, <&cpu3_intc 9>;
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
riscv,ndev = <240>;
|
|
};
|
|
|
|
clint: timer@ffdc000000 {
|
|
compatible = "thead,th1520-clint", "thead,c900-clint", "riscv,clint0";
|
|
reg = <0xff 0xdc000000 0x0 0x0000d000>;
|
|
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
|
<&cpu1_intc 3>, <&cpu1_intc 7>,
|
|
<&cpu2_intc 3>, <&cpu2_intc 7>,
|
|
<&cpu3_intc 3>, <&cpu3_intc 7>;
|
|
clint,has-no-64bit-mmio;
|
|
};
|
|
|
|
secsys_reg: secsys-reg@ffff200000 {
|
|
compatible = "syscon";
|
|
reg = <0xff 0xff200000 0x0 0x10000>;
|
|
};
|
|
|
|
nvmem_controller: efuse@ffff210000 {
|
|
compatible = "xuantie,th1520-efuse", "syscon";
|
|
reg = <0xff 0xff210000 0x0 0x10000>;
|
|
xuantie,secsys = <&secsys_reg>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EFUSE_PCLK>;
|
|
clock-names = "pclk";
|
|
|
|
gmac0_mac_address: mac-address@176 {
|
|
reg = <0xb0 6>;
|
|
};
|
|
|
|
gmac1_mac_address: mac-address@184 {
|
|
reg = <0xb8 6>;
|
|
};
|
|
};
|
|
|
|
gmac0: ethernet@ffe7070000 {
|
|
compatible = "thead,th1520-dwmac";
|
|
reg = <0xff 0xe7070000 0x0 0x2000>;
|
|
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&clk CLKGEN_GMAC0_CCLK>,
|
|
<&clk CLKGEN_GMAC0_PCLK>,
|
|
<&clk CLKGEN_GMAC_AXI_ACLK>,
|
|
<&clk CLKGEN_GMAC_AXI_PCLK>;
|
|
clock-names = "stmmaceth", "pclk", "axi_aclk","axi_pclk";
|
|
snps,pbl = <32>;
|
|
snps,fixed-burst;
|
|
snps,multicast-filter-bins = <64>;
|
|
snps,perfect-filter-entries = <32>;
|
|
snps,axi-config = <&stmmac_axi_config>;
|
|
thead,gmacapb = <&gmac0_apb>;
|
|
status = "disabled";
|
|
|
|
mdio0: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
gmac1: ethernet@ffe7060000 {
|
|
compatible = "thead,th1520-dwmac";
|
|
reg = <0xff 0xe7060000 0x0 0x2000>;
|
|
interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&clk CLKGEN_GMAC1_CCLK>,
|
|
<&clk CLKGEN_GMAC1_PCLK>,
|
|
<&clk CLKGEN_GMAC_AXI_ACLK>,
|
|
<&clk CLKGEN_GMAC_AXI_PCLK>;
|
|
clock-names = "stmmaceth", "pclk","axi_aclk","axi_pclk";
|
|
snps,pbl = <32>;
|
|
snps,fixed-burst;
|
|
snps,multicast-filter-bins = <64>;
|
|
snps,perfect-filter-entries = <32>;
|
|
snps,axi-config = <&stmmac_axi_config>;
|
|
thead,gmacapb = <&gmac1_apb>;
|
|
status = "disabled";
|
|
|
|
mdio1: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
uart0: serial@ffe7014000 {
|
|
compatible = "snps,dw-apb-uart", "light,uart0";
|
|
reg = <0xff 0xe7014000 0x0 0x100>;
|
|
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&uart_sclk>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@ffe7f00000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xff 0xe7f00000 0x0 0x100>;
|
|
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&uart_sclk>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@ffec010000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xff 0xec010000 0x0 0x100>;
|
|
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&uart_sclk>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@ffe7f04000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xff 0xe7f04000 0x0 0x100>;
|
|
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&uart_sclk>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@fff7f08000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xff 0xf7f08000 0x0 0x100>;
|
|
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&uart_sclk>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@fff7f0c000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xff 0xf7f0c000 0x0 0x100>;
|
|
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&uart_sclk>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@ffe7f20000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xff 0xe7f20000 0x0 0x1000>;
|
|
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_I2C0_PCLK>;
|
|
clock-names = "pclk";
|
|
clock-frequency = <100000>;
|
|
dma-mode;
|
|
dmas = <&dmac0 12>, <&dmac0 13>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
ss_hcnt = /bits/ 16 <0x104>;
|
|
ss_lcnt = /bits/ 16 <0xec>;
|
|
fs_hcnt = /bits/ 16 <0x37>;
|
|
fs_lcnt = /bits/ 16 <0x42>;
|
|
fp_hcnt = /bits/ 16 <0x14>;
|
|
fp_lcnt = /bits/ 16 <0x1a>;
|
|
hs_hcnt = /bits/ 16 <0x9>;
|
|
hs_lcnt = /bits/ 16 <0x11>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@ffe7f24000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xff 0xe7f24000 0x0 0x1000>;
|
|
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_I2C1_PCLK>;
|
|
clock-names = "pclk";
|
|
clock-frequency = <100000>;
|
|
dma-mode;
|
|
dmas = <&dmac0 14>, <&dmac0 15>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
ss_hcnt = /bits/ 16 <0x104>;
|
|
ss_lcnt = /bits/ 16 <0xec>;
|
|
fs_hcnt = /bits/ 16 <0x37>;
|
|
fs_lcnt = /bits/ 16 <0x42>;
|
|
fp_hcnt = /bits/ 16 <0x14>;
|
|
fp_lcnt = /bits/ 16 <0x1a>;
|
|
hs_hcnt = /bits/ 16 <0x9>;
|
|
hs_lcnt = /bits/ 16 <0x11>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@ffec00c000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xff 0xec00c000 0x0 0x1000>;
|
|
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_I2C2_PCLK>;
|
|
clock-names = "pclk";
|
|
clock-frequency = <100000>;
|
|
dma-mode;
|
|
dmas = <&dmac0 16>, <&dmac0 17>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
ss_hcnt = /bits/ 16 <0x104>;
|
|
ss_lcnt = /bits/ 16 <0xec>;
|
|
fs_hcnt = /bits/ 16 <0x37>;
|
|
fs_lcnt = /bits/ 16 <0x42>;
|
|
fp_hcnt = /bits/ 16 <0x14>;
|
|
fp_lcnt = /bits/ 16 <0x1a>;
|
|
hs_hcnt = /bits/ 16 <0x9>;
|
|
hs_lcnt = /bits/ 16 <0x11>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c3: i2c@ffec014000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xff 0xec014000 0x0 0x1000>;
|
|
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_I2C3_PCLK>;
|
|
clock-names = "pclk";
|
|
clock-frequency = <100000>;
|
|
dma-mode;
|
|
dmas = <&dmac0 18>, <&dmac0 19>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
ss_hcnt = /bits/ 16 <0x104>;
|
|
ss_lcnt = /bits/ 16 <0xec>;
|
|
fs_hcnt = /bits/ 16 <0x37>;
|
|
fs_lcnt = /bits/ 16 <0x42>;
|
|
fp_hcnt = /bits/ 16 <0x14>;
|
|
fp_lcnt = /bits/ 16 <0x1a>;
|
|
hs_hcnt = /bits/ 16 <0x9>;
|
|
hs_lcnt = /bits/ 16 <0x11>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c4: i2c@ffe7f28000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xff 0xe7f28000 0x0 0x1000>;
|
|
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_I2C4_PCLK>;
|
|
clock-names = "pclk";
|
|
clock-frequency = <100000>;
|
|
dma-mode;
|
|
dmas = <&dmac0 20>, <&dmac0 21>;
|
|
dma-names = "tx", "rx";
|
|
#dma-cells = <1>;
|
|
ss_hcnt = /bits/ 16 <0x104>;
|
|
ss_lcnt = /bits/ 16 <0xec>;
|
|
fs_hcnt = /bits/ 16 <0x37>;
|
|
fs_lcnt = /bits/ 16 <0x42>;
|
|
fp_hcnt = /bits/ 16 <0x14>;
|
|
fp_lcnt = /bits/ 16 <0x1a>;
|
|
hs_hcnt = /bits/ 16 <0x9>;
|
|
hs_lcnt = /bits/ 16 <0x11>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
audio_mbox: audio_mbox@0xffefc48000 {
|
|
compatible = "thead,th1520-audio-mbox-reg", "syscon";
|
|
reg = <0xff 0xefc48000 0x0 0x1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
gpio@ffe7f34000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xff 0xe7f34000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk CLKGEN_GPIO2_PCLK>,
|
|
<&clk CLKGEN_GPIO2_DBCLK>;
|
|
clock-names = "bus", "db";
|
|
|
|
gpio2: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <32>;
|
|
gpio-ranges = <&padctrl0_apsys 0 0 32>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
gpio@ffe7f38000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xff 0xe7f38000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk CLKGEN_GPIO3_PCLK>,
|
|
<&clk CLKGEN_GPIO3_DBCLK>;
|
|
clock-names = "bus", "db";
|
|
|
|
gpio3: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <23>;
|
|
gpio-ranges = <&padctrl0_apsys 0 32 23>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
padctrl1_apsys: pinctrl@ffe7f3c000 {
|
|
compatible = "xuantie,th1520-group2-pinctrl";
|
|
reg = <0xff 0xe7f3c000 0x0 0x1000>;
|
|
clocks = <&clk CLKGEN_PADCTRL1_APSYS_PCLK>;
|
|
clock-names = "pclk";
|
|
};
|
|
|
|
gmac0_apb: syscon@ffec003000 {
|
|
compatible = "thead,th1520-gmac-apb", "syscon";
|
|
reg = <0xff 0xec003000 0x0 0x1000>;
|
|
};
|
|
|
|
gmac1_apb: syscon@ffec004000 {
|
|
compatible = "thead,th1520-gmac-apb", "syscon";
|
|
reg = <0xff 0xec004000 0x0 0x1000>;
|
|
};
|
|
|
|
gpio@ffec005000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xff 0xec005000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk CLKGEN_GPIO0_PCLK>,
|
|
<&clk CLKGEN_GPIO0_DBCLK>;
|
|
clock-names = "bus", "db";
|
|
|
|
gpio0: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <32>;
|
|
gpio-ranges = <&padctrl1_apsys 0 0 32>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
gpio@ffec006000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xff 0xec006000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk CLKGEN_GPIO1_PCLK>,
|
|
<&clk CLKGEN_GPIO1_DBCLK>;
|
|
clock-names = "bus", "db";
|
|
|
|
gpio1: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <31>;
|
|
gpio-ranges = <&padctrl1_apsys 0 32 31>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
padctrl0_apsys: pinctrl@ffec007000 {
|
|
compatible = "xuantie,th1520-group3-pinctrl";
|
|
reg = <0xff 0xec007000 0x0 0x1000>;
|
|
clocks = <&clk CLKGEN_PADCTRL0_APSYS_PCLK>;
|
|
clock-names = "pclk";
|
|
};
|
|
|
|
pwm: pwm@ffec01c000 {
|
|
compatible = "thead,th1520-pwm";
|
|
reg = <0xff 0xec01c000 0x0 0x4000>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&osc>;
|
|
};
|
|
|
|
misc_sysreg: misc_sysreg@ffec02c000 {
|
|
compatible = "thead,th1520-misc-sysreg", "syscon";
|
|
reg = <0xff 0xec02c000 0x0 0x1000>;
|
|
};
|
|
|
|
usb: usb@ffec03f000 {
|
|
compatible = "thead,th1520-usb";
|
|
usb3-misc-regmap = <&misc_sysreg>;
|
|
reg = <0xff 0xec03f000 0x0 0x1000>;
|
|
thead,misc-sysreg = <&misc_sysreg>;
|
|
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CTRL_REF_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_PHY_REF_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_SUSPEND_CLK>;
|
|
clock-names = "drd", "ctrl", "phy", "suspend";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
usb_dwc3: usb@ffe7040000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0xff 0xe7040000 0x0 0x10000>;
|
|
interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,usb3_lpm_capable;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dmac0: dma-controller@ffefc00000 {
|
|
compatible = "xuantie,th1520-axi-dma";
|
|
reg = <0xff 0xefc00000 0x0 0x1000>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
|
|
clock-names = "core-clk", "cfgr-clk";
|
|
#dma-cells = <1>;
|
|
dma-channels = <4>;
|
|
snps,block-size = <65536 65536 65536 65536>;
|
|
snps,priority = <0 1 2 3>;
|
|
snps,dma-masters = <1>;
|
|
snps,data-width = <4>;
|
|
snps,axi-max-burst-len = <16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmac1: dma-controller@ffff340000 {
|
|
compatible = "snps,axi-dma-1.01a";
|
|
reg = <0xff 0xff340000 0x0 0x1000>;
|
|
interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
|
|
clock-names = "core-clk", "cfgr-clk";
|
|
#dma-cells = <1>;
|
|
dma-channels = <4>;
|
|
snps,block-size = <65536 65536 65536 65536>;
|
|
snps,priority = <0 1 2 3>;
|
|
snps,dma-masters = <1>;
|
|
snps,data-width = <4>;
|
|
snps,axi-max-burst-len = <16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmac2: dma-controller@ffc8000000 {
|
|
compatible = "xuantie,th1520-axi-dma";
|
|
reg = <0xff 0xc8000000 0x0 0x2000>;
|
|
interrupts = <167 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
|
|
clock-names = "core-clk", "cfgr-clk";
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
snps,block-size = <65536 65536 65536 65536
|
|
65536 65536 65536 65536
|
|
65536 65536 65536 65536
|
|
65536 65536 65536 65536>;
|
|
snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; // <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
|
snps,dma-masters = <1>;
|
|
snps,data-width = <4>;
|
|
snps,axi-max-burst-len = <16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc: mmc@ffe7080000 {
|
|
compatible = "thead,th1520-dwcmshc";
|
|
reg = <0xff 0xe7080000 0x0 0x10000>;
|
|
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
|
|
clock-names = "core", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio0: mmc@ffe7090000 {
|
|
compatible = "thead,th1520-dwcmshc";
|
|
reg = <0xff 0xe7090000 0x0 0x10000>;
|
|
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
|
|
clock-names = "core", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio1: mmc@ffe70a0000 {
|
|
compatible = "thead,th1520-dwcmshc";
|
|
reg = <0xff 0xe70a0000 0x0 0x10000>;
|
|
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
|
|
clock-names = "core", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer0: timer@ffefc32000 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xefc32000 0x0 0x14>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer1: timer@ffefc32014 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xefc32014 0x0 0x14>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer2: timer@ffefc32028 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xefc32028 0x0 0x14>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer3: timer@ffefc3203c {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xefc3203c 0x0 0x14>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer4: timer@ffffc33000 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xffc33000 0x0 0x14>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer5: timer@ffffc33014 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xffc33014 0x0 0x14>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer6: timer@ffffc33028 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xffc33028 0x0 0x14>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer7: timer@ffffc3303c {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xffc3303c 0x0 0x14>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc: rtc@fffff40000 {
|
|
compatible = "snps,dw-apb-rtc";
|
|
reg = <0xff 0xfff40000 0x0 0x1000>;
|
|
interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc_32k>;
|
|
clock-names = "osc_32k";
|
|
wakeup-source;
|
|
prescaler = <0x8000>;
|
|
status = "okay";
|
|
};
|
|
|
|
gpio@fffff41000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xff 0xfff41000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
aogpio: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&padctrl_aosys 0 9 16>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
padctrl_aosys: pinctrl@fffff4a000 {
|
|
compatible = "xuantie,th1520-group1-pinctrl";
|
|
reg = <0xff 0xfff4a000 0x0 0x2000>;
|
|
clocks = <&aonsys_clk>;
|
|
};
|
|
|
|
padctrl_audiosys: pinctrl@ffcb01d000 {
|
|
compatible = "xuantie,th1520-group4-pinctrl";
|
|
reg = <0xff 0xcb01d000 0x0 0x2000>;
|
|
clocks = <&audiosys_clk>;
|
|
};
|
|
|
|
pvt: pvt@fffff4e000 {
|
|
compatible = "moortec,mr75203";
|
|
reg = <0xff 0xfff4e000 0x0 0x80>,
|
|
<0xff 0xfff4e080 0x0 0x100>,
|
|
<0xff 0xfff4e180 0x0 0x680>,
|
|
<0xff 0xfff4e800 0x0 0x600>;
|
|
reg-names = "common", "ts", "pd", "vm";
|
|
clocks = <&aonsys_clk>;
|
|
#thermal-sensor-cells = <1>;
|
|
moortec,ts-coeff-h = <220000>;
|
|
moortec,ts-coeff-g = <42740>;
|
|
moortec,ts-coeff-j = <0xFFFFFF60>; // -160
|
|
moortec,ts-coeff-cal5 = <4094>;
|
|
};
|
|
|
|
gpio@fffff52000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xff 0xfff52000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gpio4: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <23>;
|
|
gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
bmu: ddr-pmu@ffff008000 {
|
|
compatible = "xuantie,th1520-ddr-pmu";
|
|
reg = <0xff 0xff008000 0x0 0x800
|
|
0xff 0xff008800 0x0 0x800
|
|
0xff 0xff009000 0x0 0x800
|
|
0xff 0xff009800 0x0 0x800
|
|
0xff 0xff00a000 0x0 0x800>;
|
|
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
mbox_910t: mbox@ffffc38000 {
|
|
compatible = "xuantie,th1520-mbox";
|
|
reg = <0xff 0xffc38000 0x0 0x4000>,
|
|
<0xff 0xffc44000 0x0 0x1000>,
|
|
<0xff 0xffc4c000 0x0 0x1000>,
|
|
<0xff 0xffc54000 0x0 0x1000>;
|
|
reg-names = "local_base",
|
|
"remote_icu0",
|
|
"remote_icu1",
|
|
"remote_icu2";
|
|
interrupt-controller;
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "ipg";
|
|
icu_cpu_id = <0>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
mbox_910r: mbox@ffefc53000 {
|
|
compatible = "xuantie,th1520-mbox-r";
|
|
reg = <0xff 0xefc53000 0x0 0x4000>,
|
|
<0xff 0xefc3f000 0x0 0x1000>,
|
|
<0xff 0xefc47000 0x0 0x1000>,
|
|
<0xff 0xefc4f000 0x0 0x1000>;
|
|
reg-names = "local_base",
|
|
"remote_icu0",
|
|
"remote_icu1",
|
|
"remote_icu2";
|
|
interrupt-controller;
|
|
clocks = <&apb_clk>;
|
|
clock-names = "ipg";
|
|
icu_cpu_id = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
adc: adc@0xfffff51000 {
|
|
compatible = "thead,th1520-adc";
|
|
reg = <0xff 0xfff51000 0x0 0x1000>;
|
|
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&aonsys_clk>;
|
|
clock-names = "adc";
|
|
/* ADC pin is proprietary,no need to config pinctrl */
|
|
status = "disabled";
|
|
};
|
|
|
|
visys_reg: visys-reg@ffe4040000 {
|
|
compatible = "thead,th1520-visys-reg", "syscon";
|
|
reg = <0xff 0xe4040000 0x0 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vosys_reg: vosys-reg@ffef528000 {
|
|
compatible = "xuantie,th1520-vosys-reg", "syscon";
|
|
reg = <0xff 0xef528000 0x0 0x1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
dsi0: dw-mipi-dsi0@ffef500000 {
|
|
compatible = "xuantie,th1520-mipi-dsi", "simple-bus", "syscon";
|
|
reg = <0xff 0xef500000 0x0 0x10000>;
|
|
status = "disabled";
|
|
|
|
dphy_0: dsi0-dphy {
|
|
compatible = "xuantie,th1520-mipi-dphy";
|
|
regmap = <&dsi0>;
|
|
vosys-regmap = <&vosys_reg>;
|
|
clocks = <&vosys_clk_gate TH1520_CLKGEN_MIPIDSI0_REFCLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_MIPIDSI0_CFG_CLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_MIPIDSI0_PCLK>,
|
|
<&clk OSC_24M>,
|
|
<&clk OSC_24M>;
|
|
clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
dhost_0: dsi0-host {
|
|
compatible = "verisilicon,dw-mipi-dsi";
|
|
regmap = <&dsi0>;
|
|
interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&vosys_clk_gate TH1520_CLKGEN_MIPIDSI0_PCLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_MIPIDSI0_PIXCLK>;
|
|
clock-names = "pclk", "pixclk";
|
|
phys = <&dphy_0>;
|
|
phy-names = "dphy";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
dsi1: dw-mipi-dsi1@ffef510000 {
|
|
compatible = "xuantie,th1520-mipi-dsi", "simple-bus", "syscon";
|
|
reg = <0xff 0xef510000 0x0 0x10000>;
|
|
status = "disabled";
|
|
|
|
dphy_1: dsi1-dphy {
|
|
compatible = "xuantie,th1520-mipi-dphy";
|
|
regmap = <&dsi1>;
|
|
vosys-regmap = <&vosys_reg>;
|
|
clocks = <&vosys_clk_gate TH1520_CLKGEN_MIPIDSI1_REFCLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_MIPIDSI1_CFG_CLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_MIPIDSI1_PCLK>,
|
|
<&clk OSC_24M>,
|
|
<&clk OSC_24M>;
|
|
clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
dhost_1: dsi1-host {
|
|
compatible = "verisilicon,dw-mipi-dsi";
|
|
regmap = <&dsi1>;
|
|
interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&vosys_clk_gate TH1520_CLKGEN_MIPIDSI1_PCLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_MIPIDSI1_PIXCLK>;
|
|
clock-names = "pclk", "pixclk";
|
|
phys = <&dphy_1>;
|
|
phy-names = "dphy";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
hdmi_tx: dw-hdmi-tx@ffef540000 {
|
|
compatible = "xuantie,th1520-hdmi-tx";
|
|
reg = <0xff 0xef540000 0x0 0x40000>;
|
|
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&vosys_clk_gate TH1520_CLKGEN_HDMI_PCLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_HDMI_SFR_CLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_HDMI_CEC_CLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_HDMI_PIXCLK>;
|
|
clock-names = "iahb", "isfr", "cec", "pixclk";
|
|
reg-io-width = <4>;
|
|
phy_version = <301>;
|
|
/* TODO: add phy property */
|
|
status = "disabled";
|
|
};
|
|
|
|
dpu: dc8200@ffef600000 {
|
|
compatible = "verisilicon,dc8200";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xff 0xef600000 0x0 0x100>,
|
|
<0xff 0xef600800 0x0 0x2000>,
|
|
<0xff 0xef630010 0x0 0x60>;
|
|
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
|
|
vosys-regmap = <&vosys_reg>;
|
|
clocks = <&vosys_clk_gate TH1520_CLKGEN_DPU_CCLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_DPU_PIXCLK0>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_DPU_PIXCLK1>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_DPU_ACLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_DPU_HCLK>,
|
|
<&clk DPU0_PLL_DIV_CLK>,
|
|
<&clk DPU1_PLL_DIV_CLK>,
|
|
<&clk DPU0_PLL_FOUTPOSTDIV>,
|
|
<&clk DPU1_PLL_FOUTPOSTDIV>;
|
|
clock-names = "core_clk", "pix_clk0", "pix_clk1",
|
|
"axi_clk", "cfg_clk", "pixclk0",
|
|
"pixclk1", "dpu0_pll_foutpostdiv",
|
|
"dpu1_pll_foutpostdiv";
|
|
status = "okay";
|
|
|
|
dpu_disp0: port@0 {
|
|
reg = <0>;
|
|
|
|
disp0_out: endpoint {
|
|
remote-endpoint = <&enc0_in>;
|
|
};
|
|
};
|
|
|
|
dpu_disp1: port@1 {
|
|
reg = <1>;
|
|
|
|
disp1_out: endpoint {
|
|
remote-endpoint = <&enc1_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
aon_suspend_ctrl: aon_suspend_ctrl {
|
|
compatible = "thead,th1520-aon-suspend-ctrl";
|
|
status = "okay";
|
|
};
|
|
|
|
sys_reg: sys-reg@ffef010100 {
|
|
compatible = "xuantie,th1520-sys-reg";
|
|
reg = <0xff 0xef010100 0x0 0x100>;
|
|
status = "okay";
|
|
};
|
|
|
|
dspsys_reg: dspsys-reg@ffef040000 {
|
|
compatible = "thead,th1520-dspsys-reg", "syscon";
|
|
reg = <0xff 0xef040000 0x0 0x1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
miscsys_reg: miscsys-reg@ffec02c000 {
|
|
compatible = "thead,th1520-miscsys-reg", "syscon";
|
|
reg = <0xff 0xec02c000 0x0 0x1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
tee_miscsys_reg: tee_miscsys-reg@fffc02d000 {
|
|
compatible = "thead,th1520-miscsys-reg", "syscon";
|
|
reg = <0xff 0xfc02d000 0x0 0x1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
audio_cpr: audio_cpr@ffcb000000 {
|
|
compatible = "thead,th1520-audio-cpr-reg", "syscon";
|
|
reg = <0xff 0xcb000000 0x0 0x1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
clk: clock-controller@ffef010000 {
|
|
compatible = "thead,th1520-fm-ree-clk";
|
|
reg = <0xff 0xef010000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&osc_32k>, <&osc>, <&rc_24m>;
|
|
clock-names = "osc_32k", "osc_24m", "rc_24m";
|
|
status = "okay";
|
|
};
|
|
|
|
visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
|
|
compatible = "thead,visys-gate-controller";
|
|
visys-regmap = <&visys_reg>;
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
vpsys_clk_gate: vpsys-clk-gate@ffecc30000 { /* VP_SYSREG_R */
|
|
compatible = "thead,vpsys-gate-controller";
|
|
reg = <0xff 0xecc30000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */
|
|
compatible = "thead,vosys-gate-controller";
|
|
reg = <0xff 0xef528000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
dspsys_clk_gate: dspsys-clk-gate {
|
|
compatible = "thead,dspsys-gate-controller";
|
|
dspsys-regmap = <&dspsys_reg>;
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
audiosys_clk_gate: audiosys-clk-gate {
|
|
compatible = "thead,audiosys-gate-controller";
|
|
audiosys-regmap = <&audio_cpr>;
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
miscsys_clk_gate: miscsys-clk-gate {
|
|
compatible = "thead,miscsys-gate-controller";
|
|
miscsys-regmap = <&miscsys_reg>;
|
|
tee-miscsys-regmap = <&tee_miscsys_reg>;
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
rst: reset-controller@ffef014000 {
|
|
compatible = "xuantie,th1520-reset", "syscon";
|
|
reg = <0xff 0xef014000 0x0 0x1000>;
|
|
#reset-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
vpsys_rst: vpsys-reset-controller@ffecc30000 {
|
|
compatible = "xuantie,th1520-vpsys-reset","syscon";
|
|
reg = <0xff 0xecc30000 0x0 0x1000>;
|
|
#reset-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
audiosys_rst: audiosys-reset-controller@ffcb000000 {
|
|
compatible = "xuantie,th1520-audiosys-reset","syscon";
|
|
reg = <0xff 0xcb000000 0x0 0x1000>;
|
|
#reset-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
spi: spi@ffe700c000 {
|
|
compatible = "snps,dw-apb-ssi";
|
|
reg = <0xff 0xe700c000 0x0 0x1000>;
|
|
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_SPI_SSI_CLK>,
|
|
<&clk CLKGEN_SPI_PCLK>;
|
|
clock-names = "sclk", "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi0: spi@ffea000000 {
|
|
compatible = "snps,dw-apb-ssi-quad";
|
|
reg = <0xff 0xea000000 0x0 0x1000>;
|
|
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_QSPI0_SSI_CLK>,
|
|
<&clk CLKGEN_QSPI0_PCLK>;
|
|
clock-names = "sclk", "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi1: spi@fff8000000 {
|
|
compatible = "snps,dw-apb-ssi-quad";
|
|
reg = <0xff 0xf8000000 0x0 0x1000>;
|
|
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_QSPI1_SSI_CLK>,
|
|
<&clk CLKGEN_QSPI1_PCLK>;
|
|
clock-names = "sclk", "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
th1520_event: th1520-event {
|
|
compatible = "thead,th1520-event";
|
|
aon-iram-regmap = <&aon_iram>;
|
|
status = "okay";
|
|
};
|
|
|
|
watchdog0: watchdog@ffefc30000 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xff 0xefc30000 0x0 0x1000>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_WDT0_PCLK>;
|
|
clock-names = "tclk";
|
|
resets = <&rst TH1520_RESET_WDT0>;
|
|
status = "okay";
|
|
};
|
|
|
|
watchdog1: watchdog@ffefc31000 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xff 0xefc31000 0x0 0x1000>;
|
|
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk CLKGEN_WDT1_PCLK>;
|
|
clock-names = "tclk";
|
|
resets = <&rst TH1520_RESET_WDT1>;
|
|
status = "okay";
|
|
};
|
|
|
|
watchdog_aon: watchdog-aon {
|
|
compatible = "xuantie,th1520-aon-wdt";
|
|
status = "okay";
|
|
};
|
|
|
|
regdump: th1520-regdump {
|
|
compatible = "xuantie,th1520-regdump";
|
|
status = "disabled";
|
|
};
|
|
|
|
vdec_opp_table: opp_table_vdec {
|
|
compatible = "operating-points-v2";
|
|
video-4k-minfreq = <594000000>;
|
|
qos-mid-minfreq = <297000000>;
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <158400000>;
|
|
opp-microvolt = <875000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <198000000>;
|
|
opp-microvolt = <875000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <237600000>;
|
|
opp-microvolt = <875000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <264000000>;
|
|
opp-microvolt = <887500>;
|
|
};
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <297000000>;
|
|
opp-microvolt = <937500>;
|
|
};
|
|
opp05 {
|
|
opp-hz = /bits/ 64 <396000000>;
|
|
opp-microvolt = <1012500>;
|
|
};
|
|
opp06 {
|
|
opp-hz = /bits/ 64 <475200000>;
|
|
opp-microvolt = <1037500>;
|
|
};
|
|
opp07 {
|
|
opp-hz = /bits/ 64 <594000000>;
|
|
opp-microvolt = <1050000>;
|
|
};
|
|
};
|
|
|
|
venc_opp_table: opp_table_venc {
|
|
compatible = "operating-points-v2";
|
|
qos-mid-minfreq = <250000000>;
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <250000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <333300000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
};
|
|
};
|
|
|
|
vdec: vdec@ffecc00000 {
|
|
compatible = "xuantie,th1520-vc8000d";
|
|
reg = <0xff 0xecc00000 0x0 0x8000>;
|
|
interrupts = <131 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&pd TH1520_AON_VDEC_PD>;
|
|
clocks = <&vpsys_clk_gate TH1520_VPSYS_VDEC_ACLK>,
|
|
<&vpsys_clk_gate TH1520_VPSYS_VDEC_CCLK>,
|
|
<&vpsys_clk_gate TH1520_VPSYS_VDEC_PCLK>;
|
|
clock-names = "aclk", "cclk", "pclk";
|
|
operating-points-v2 = <&vdec_opp_table>;
|
|
status = "okay";
|
|
};
|
|
|
|
venc: venc@ffecc10000 {
|
|
compatible = "xuantie,th1520-vc8000e";
|
|
reg = <0xff 0xecc10000 0x0 0x8000>;
|
|
interrupts = <133 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&pd TH1520_AON_VENC_PD>;
|
|
clocks = <&vpsys_clk_gate TH1520_VPSYS_VENC_ACLK>,
|
|
<&vpsys_clk_gate TH1520_VPSYS_VENC_CCLK>,
|
|
<&vpsys_clk_gate TH1520_VPSYS_VENC_PCLK>;
|
|
clock-names = "aclk", "cclk", "pclk";
|
|
operating-points-v2 =<&venc_opp_table>;
|
|
status = "okay";
|
|
};
|
|
|
|
g2d_opp_table:g2d-opp-table {
|
|
compatible = "operating-points-v2";
|
|
video-4k-minfreq = <396000000>;
|
|
qos-mid-minfreq = <198000000>;
|
|
|
|
opp-49500000 {
|
|
opp-hz = /bits/ 64 <49500000>;
|
|
};
|
|
opp-99000000 {
|
|
opp-hz = /bits/ 64 <99000000>;
|
|
};
|
|
opp-198000000 {
|
|
opp-hz = /bits/ 64 <198000000>;
|
|
};
|
|
opp-396000000 {
|
|
opp-hz = /bits/ 64 <396000000>;
|
|
};
|
|
};
|
|
|
|
g2d: gc620@ffecc80000 {
|
|
compatible = "xuantie,th1520-gc620";
|
|
reg = <0xff 0xecc80000 0x0 0x40000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_2d";
|
|
clocks = <&vpsys_clk_gate TH1520_VPSYS_G2D_PCLK>,
|
|
<&vpsys_clk_gate TH1520_VPSYS_G2D_ACLK>,
|
|
<&vpsys_clk_gate TH1520_VPSYS_G2D_CCLK>;
|
|
clock-names = "pclk", "aclk", "cclk";
|
|
operating-points-v2 = <&g2d_opp_table>;
|
|
status = "okay";
|
|
};
|
|
|
|
vidmem: vidmem@ffecc08000 {
|
|
compatible = "xuantie,th1520-vidmem";
|
|
reg = <0xff 0xecc08000 0x0 0x1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
bm_visys: bm_visys@ffe4040000 {
|
|
compatible = "xuantie,th1520-bm-visys";
|
|
reg = <0xff 0xe4040000 0x0 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bm_csi0: csi@ffe4000000{ //CSI2
|
|
compatible = "xuantie,th1520-bm-csi";
|
|
reg = < 0xff 0xe4000000 0x0 0x10000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
|
|
dphyglueiftester = <0x180>;
|
|
sysreg_mipi_csi_ctrl = <0x140>;
|
|
clocks = <&visys_clk_gate TH1520_CLKGEN_MIPI_CSI0_PCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI0_PIXCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI0_CFG_CLK>;
|
|
clock-names = "pclk", "pixclk", "cfg_clk";
|
|
phy_name = "CSI_4LANE";
|
|
status = "disabled";
|
|
};
|
|
|
|
csia_reg: visys-reg@ffe4020000 {
|
|
compatible = "xuantie,th1520-visys-reg", "syscon";
|
|
reg = < 0xff 0xe4020000 0x0 0x10000>;
|
|
status = "okay";
|
|
};
|
|
|
|
csib_reg: visys-reg@ffe4010000{
|
|
compatible = "xuantie,th1520-visys-reg", "syscon";
|
|
reg = < 0xff 0xe4010000 0x0 0x10000>;
|
|
status = "okay";
|
|
};
|
|
|
|
bm_csi1: csi@ffe4010000{ //CSI2X2_B
|
|
compatible = "xuantie,th1520-bm-csi";
|
|
reg = < 0xff 0xe4010000 0x0 0x10000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <126 IRQ_TYPE_LEVEL_HIGH>; // 110 + 16 int_mipi_csi2x2_int0
|
|
dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
|
|
sysreg_mipi_csi_ctrl = <0x148>;
|
|
visys-regmap = <&visys_reg>;
|
|
csia-regmap = <&csia_reg>;
|
|
clocks = <&visys_clk_gate TH1520_CLKGEN_MIPI_CSI1_PCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI1_PIXCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI1_CFG_CLK>;
|
|
clock-names = "pclk", "pixclk", "cfg_clk";
|
|
phy_name = "CSI_B";
|
|
status = "disabled";
|
|
};
|
|
|
|
bm_csi2: csi@ffe4020000{ //CSI2X2_A
|
|
compatible = "xuantie,th1520-bm-csi";
|
|
reg = < 0xff 0xe4020000 0x0 0x10000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <127 IRQ_TYPE_LEVEL_HIGH>;
|
|
dphyglueiftester = <0x184>;
|
|
sysreg_mipi_csi_ctrl = <0x144>;
|
|
sysreg_mipi_csi_fifo_ctrl = <0x14c>;
|
|
csib-regmap = <&csib_reg>;
|
|
clocks = <&visys_clk_gate TH1520_CLKGEN_MIPI_CSI2_PCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI2_PIXCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI2_CFG_CLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI1_PCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI1_PIXCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_MIPI_CSI1_CFG_CLK>;
|
|
clock-names = "pclk", "pixclk", "cfg_clk", "pclk1", "pixclk1", "cfg_clk1";
|
|
phy_name = "CSI_A";
|
|
status = "disabled";
|
|
};
|
|
|
|
isp0: isp@ffe4100000 {
|
|
compatible = "xuantie,th1520-isp";
|
|
reg = <0xff 0xe4100000 0x0 0x10000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <117 IRQ_TYPE_LEVEL_HIGH>,<118 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&visys_clk_gate TH1520_CLKGEN_ISP0_ACLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP0_HCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP0_PIXELCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP0_CLK>;
|
|
clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
isp1: isp@ffe4110000 {
|
|
compatible = "xuantie,th1520-isp";
|
|
reg = <0xff 0xe4110000 0x0 0x10000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <120 IRQ_TYPE_LEVEL_HIGH>,<121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&visys_clk_gate TH1520_CLKGEN_ISP0_ACLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP0_HCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP0_PIXELCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP1_CLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP1_PIXELCLK>;
|
|
clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
isp_ry0: isp_ry@ffe4120000 {
|
|
compatible = "xuantie,th1520-isp_ry";
|
|
reg = <0xff 0xe4120000 0x0 0x10000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <123 IRQ_TYPE_LEVEL_HIGH>,<124 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&visys_clk_gate TH1520_CLKGEN_ISP_RY_ACLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP_RY_HCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_ISP_RY_CCLK>;
|
|
clock-names = "aclk", "hclk", "cclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
dewarp: dewarp@ffe4130000 {
|
|
compatible = "xuantie,th1520-dewarp";
|
|
reg = <0xff 0xe4130000 0x0 0x10000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <98 IRQ_TYPE_LEVEL_HIGH>,<99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&visys_clk_gate TH1520_CLKGEN_DW200_ACLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_DW200_HCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_DW200_CLK_VSE>,
|
|
<&visys_clk_gate TH1520_CLKGEN_DW200_CLK_DWE>;
|
|
clock-names = "aclk", "hclk", "vseclk", "dweclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
dec400_isp0: dec400@ffe4060000 {
|
|
compatible = "xuantie,th1520-dec400";
|
|
reg = <0xff 0xe4060000 0x0 0x8000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dec400_isp1: dec400@ffe4068000 {
|
|
compatible = "xuantie,th1520-dec400";
|
|
reg = <0xff 0xe4068000 0x0 0x8000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dec400_isp2: dec400@ffe4070000 {
|
|
compatible = "xuantie,th1520-dec400";
|
|
reg = <0xff 0xe4070000 0x0 0x8000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
vi_pre: vi_pre@ffe4030000 {
|
|
compatible = "xuantie,th1520-vi_pre";
|
|
reg = <0xff 0xe4030000 0x0 0x1000>;
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&visys_clk_gate TH1520_CLKGEN_VIPRE_ACLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_VIPRE_PCLK>,
|
|
<&visys_clk_gate TH1520_CLKGEN_VIPRE_PIXELCLK>;
|
|
clock-names ="aclk", "pclk", "pixclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
xtensa_dsp: dsp@01{
|
|
compatible = "xuantie,dsp-hw-common";
|
|
reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */
|
|
status = "disabled";
|
|
};
|
|
|
|
xtensa_dsp0: dsp@0 {
|
|
compatible = "cdns,xrp-hw-simple";
|
|
reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */
|
|
0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */
|
|
0xff 0xef048000 0x0 0x008000 /* DSP shared memory */
|
|
0xff 0xe0180000 0x0 0x040000>; /* DSP TCM*/
|
|
dsp = <0>;
|
|
dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
|
|
dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
|
|
device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
|
|
device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
|
|
device-irq-mode = <1>; /*level trigger*/
|
|
host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
|
|
host-irq-mode = <1>; /*level trigger */
|
|
host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <156 IRQ_TYPE_LEVEL_HIGH>;
|
|
#cooling-cells = <2>;
|
|
firmware-name = "xrp0.elf";
|
|
clocks = <&dspsys_clk_gate CLKGEN_DSP0_PCLK>,
|
|
<&dspsys_clk_gate CLKGEN_DSP0_CCLK>;
|
|
clock-names = "pclk", "cclk";
|
|
status = "disabled";
|
|
operating-points-v2 = <&dsp_opp_table>;
|
|
dynamic-power-coefficient = <1000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
|
|
0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
|
|
0x00 0xfa000000 0xff 0xe0000000 0x00180000
|
|
0x00 0xe0180000 0xff 0xe0180000 0x00040000
|
|
0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
|
|
dsp@0 {
|
|
ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
|
|
0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
|
|
0x00 0xfa000000 0xff 0xe0000000 0x00180000
|
|
0x00 0xe0180000 0xff 0xe0180000 0x00040000
|
|
0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
|
|
};
|
|
};
|
|
|
|
xtensa_dsp1: dsp@1 {
|
|
compatible = "cdns,xrp-hw-simple";
|
|
reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */
|
|
0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */
|
|
0xff 0xef050000 0x0 0x008000 /* DSP shared memory */
|
|
0xff 0xe01C0000 0x0 0x040000>;/* DSP TCM*/
|
|
dsp = <1>;
|
|
dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
|
|
dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
|
|
device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
|
|
device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
|
|
device-irq-mode = <1>; /*level trigger*/
|
|
host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
|
|
host-irq-mode = <1>; /*level trigger */
|
|
host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
|
|
interrupt-parent = <&plic>;
|
|
interrupts = <157 IRQ_TYPE_LEVEL_HIGH>;
|
|
firmware-name = "xrp1.elf";
|
|
#cooling-cells = <2>;
|
|
clocks = <&dspsys_clk_gate CLKGEN_DSP1_PCLK>,
|
|
<&dspsys_clk_gate CLKGEN_DSP1_CCLK>;
|
|
clock-names = "pclk", "cclk";
|
|
status = "disabled";
|
|
operating-points-v2 = <&dsp_opp_table>;
|
|
dynamic-power-coefficient = <1000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
|
|
0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
|
|
0x00 0xfa000000 0xff 0xe0000000 0x00180000
|
|
0x00 0xe0180000 0xff 0xe01C0000 0x00040000
|
|
0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
|
|
dsp@0 {
|
|
ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
|
|
0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
|
|
0x00 0xfa000000 0xff 0xe0000000 0x00180000
|
|
0x00 0xe0180000 0xff 0xe01C0000 0x00040000
|
|
0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
|
|
};
|
|
};
|
|
|
|
|
|
dsp_opp_table: dsp_opp_table {
|
|
compatible = "operating-points-v2";
|
|
qos-mid-minfreq = <500000000>;
|
|
|
|
opp-125000000 {
|
|
opp-hz = /bits/ 64 <125000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
|
|
opp-250000000 {
|
|
opp-hz = /bits/ 64 <250000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
|
|
opp-500000000 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp-1000000000 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <800000>;
|
|
opp-suspend;
|
|
};
|
|
};
|
|
|
|
npu: vha@fffc800000 {
|
|
compatible = "img,ax3386-nna";
|
|
reg = <0xff 0xfc800000 0x0 0x100000>;
|
|
interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "npuirq";
|
|
#cooling-cells = <2>;
|
|
dynamic-power-coefficient = <1600>;
|
|
power-domains = <&pd TH1520_AON_NPU_PD>;
|
|
clocks = <&clk CLKGEN_TOP_APB_SX_PCLK>,
|
|
<&clk CLKGEN_TOP_AXI4S_ACLK>,
|
|
<&clk NPU_CCLK>,
|
|
<&clk GMAC_PLL_FOUTPOSTDIV>,
|
|
<&clk NPU_CCLK_OUT_DIV>;
|
|
clock-names = "pclk", "aclk", "cclk",
|
|
"gmac_pll_foutpostdiv",
|
|
"npu_cclk_out_div";
|
|
operating-points-v2 = <&npu_opp_table>;
|
|
vha_clk_rate = <1000000000>;
|
|
ldo_vha-supply = <&npu>;
|
|
dma-mask = <0xff 0xffffffff>;
|
|
resets = <&rst TH1520_RESET_NPU>;
|
|
status = "disabled";
|
|
};
|
|
|
|
npu_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
qos-mid-minfreq = <594000000>;
|
|
|
|
opp-1000000000 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp-792000000 {
|
|
opp-hz = /bits/ 64 <792000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp-594000000 {
|
|
opp-hz = /bits/ 64 <594000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp-475200000 {
|
|
opp-hz = /bits/ 64 <475200000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp-396000000 {
|
|
opp-hz = /bits/ 64 <396000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
};
|
|
|
|
gpu: gpu@ffef400000 {
|
|
compatible = "img,gpu";
|
|
reg = <0xff 0xef400000 0x0 0x100000>;
|
|
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gpuirq";
|
|
vosys-regmap = <&vosys_reg>;
|
|
power-domains = <&pd TH1520_AON_GPU_PD>;
|
|
clocks = <&vosys_clk_gate TH1520_CLKGEN_GPU_CORE_CLK>,
|
|
<&vosys_clk_gate TH1520_CLKGEN_GPU_CFG_ACLK>;
|
|
clock-names = "cclk", "aclk";
|
|
gpu_clk_rate = <18000000>;
|
|
dma-mask = <0xf 0xffffffff>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iso7816: iso7816-card@fff7f30000 {
|
|
compatible = "xuantie,th1520-iso7816-card";
|
|
reg = <0xff 0xf7f30000 0x0 0x4000>;
|
|
interrupts = <69 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
eip_28: eip-28@ffff300000 {
|
|
compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28";
|
|
reg = <0xff 0xff300000 0x0 0x40000>;
|
|
interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<147 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SI_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SII_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SIII_CLK>,
|
|
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP150B_HCLK>;
|
|
clock-names = "120si_clk","120sii_clk","120siii_clk","hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
hwspinlock: hwspinlock@ffefc10000 {
|
|
compatible = "th1520,hwspinlock";
|
|
reg = <0xff 0xefc10000 0x0 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|