OERV-BSP/kernel-zhihe-a210
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Release develop 251015

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hongyi
2025-10-15 12:49:35 +08:00
parent fee9d0a7ce
commit e8e2710771
6 changed files with 88 additions and 3 deletions
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49
arch/riscv/boot/dts/zhihe/a210-dev.dts Normal file → Executable file
View File

@@ -1,5 +1,6 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "a210-soc-core.dtsi"
#include "a210-soc-peri.dtsi"
#include "a210-platform-dev.dtsi"
@@ -37,6 +38,7 @@
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
aoi2c1 = &aoi2c1;
can0 = &can0;
can1 = &can1;
@@ -148,6 +150,17 @@
slew-rate = <0>;
};
};
aoi2c1_pins: aoi2c1-0 {
i2c-pins {
pins = "AOI2C1_SCL", "AOI2C1_SDA";
function = "aoi2c1";
bias-disable;
drive-strength = <7>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
};
&peri1_padctrl {
@@ -573,6 +586,7 @@
compatible = "awinic,aw87565_pa";
reg = <0x5b>;
sound-name-prefix = "AW87565_PA2";
reset-gpios = <&aw9535_0 8 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
@@ -589,6 +603,41 @@
clock-frequency = <400000>;
};
&aoi2c1 {
pinctrl-names = "default";
pinctrl-0 = <&aoi2c1_pins>;
clock-frequency = <400000>;
status = "okay";
aw9535_0: gpio@20 {
compatible = "awinic,aw9535";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
interrupt-parent = <&ao_gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
gpio-line-names =
"CSI1_PWDN_IO0", "CSI1_RST_IO1", "CSI1_FSIN_IO2", "CSI0_PWDN_IO3", // index 0..3
"CSI0_RST_IO4", "CSI0_FSIN_IO5", "PCIE_X1_PRSNT_L_IO6", "PCIE_X4_PRSNT_L_IO7", // index 4..7
"AUDIO1_PARST0_IO8", "AUDIO_ADC1_INT_IO9", "AUDIO_ADC0_INT_IO10", "HP_CTL_H_IO11", // index 8..11
"SIT91211_SSC_EN_IO12","DISP_RST_IO13","SWITCH3_SEL_IO14","SWITCH1_SEL_IO15"; // index 12..15
};
aw9535_1: gpio@21 {
compatible = "awinic,aw9535";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
gpio-line-names =
"PCIE_BAT_EN_IO0", "AUDIO_3V3_PWREN_IO1", "AUDIO_1V8_PWREN_IO2", "MIPI_CSI0_PWREN_IO3", // index 0..3
"MIPI_CSI1_PWREN_IO4", "MIPI_TP_PWREN_IO5", "PCIE_3V3_EN_IO6", "PCIE_12V_EN_IO7", // index 4..7
"USBCON_PWREN_IO8", "USBCON1_PWREN_IO9", "PCIE_3V3_AUX_EN_IO10", "SDIO_3V3_PWREN_IO11", // index 8..11
"SDIO_1V8_PWREN_IO12","SIT91211_3V3_EN_IO13","MIPI_DSI_PWREN_IO14","BL_EN_IO15"; // index 12..15
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;

14
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi Normal file → Executable file
View File

@@ -1045,6 +1045,20 @@
status = "okay";
};
aoi2c1: i2c@30891000{
compatible = "snps,designware-i2c";
reg = <0x00 0x30891000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <20>;
//clocks = <&clk_peri PERI2_I2C7_IC_CLK_EN>, <&clk_peri PERI2_I2C7_PCLK_EN>;
clocks = <&aon_110m>;
clock-names = "ref", "pclk";
//power-domains = <&power_peri2>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
vdec: vdec@0006800000 {
compatible = "zhihe,vpu-vc9000d";
address-cells = <2>;