Release develop 251101

arch/riscv/boot/dts/zhihe/Makefile

@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 
-dtb-$(CONFIG_ARCH_ZHIHE) += a210-emu.dtb a210-emu-d2d.dtb a210-som-v1.dtb a210-evb.dtb a210-dev.dtb a210-evb-d2d.dtb
+dtb-$(CONFIG_ARCH_ZHIHE) += a210-emu.dtb a210-emu-d2d.dtb a210-som-v1.dtb a210-evb.dtb a210-dev.dtb a210-evb-d2d.dtb a210-evb-sec.dtb a210-dev-sec.dtb

arch/riscv/boot/dts/zhihe/a210-dev-sec.dts

@@ -0,0 +1,2 @@
+#include "a210-dev.dts"
+#include "a210-sec-tee.dtsi"

arch/riscv/boot/dts/zhihe/a210-dev.dts

@@ -257,7 +257,7 @@
 	};
 	pcie_x1_pins: pcie_x1-1 {
 		pcie_x1-pins {
-			pins = "GPIO0_24", "GPIO0_25", "GPIO0_26", "GPIO0_27";
+			pins = "GPIO0_18", "GPIO0_19", "GPIO0_20", "GPIO0_21";
 			function = "pcie_x1";
 			bias-disable;
 			drive-strength = <7>;
@@ -540,6 +540,7 @@
 	spi-max-frequency = <55000000>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&qspi0_pins>;
+	status = "disabled";
 
 	spi_norflash@0 {
 		compatible = "jedec,spi-nor";
@@ -688,6 +689,12 @@
 &rp3x1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_x1_pins>;
+	minipcie-1v5-pwren-gpios = 	<&aw9535_0  6 GPIO_ACTIVE_HIGH>;
+	minipcie-3v3-pwren-gpios = 	<&aw9535_0  7 GPIO_ACTIVE_HIGH>;
+	minipcie-perst-gpios = 	        <&aw9535_0 15 GPIO_ACTIVE_HIGH>;
+	pcie-clk-en-gpios = 		<&aw9535_0 12 GPIO_ACTIVE_HIGH>;
+	pcie-clk-pwren-gpios = 		<&aw9535_1 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
 };
 
 &dm3x4 {
@@ -773,3 +780,11 @@
 	pinctrl-0 = <&usb3_pins>;
 	typec-pwren-gpios = <&gpio0_porta 27 GPIO_ACTIVE_HIGH>;
 };
+
+&sata {
+	m2-sata-3v3-pwren-gpios = 	<&aw9535_0 14 GPIO_ACTIVE_HIGH>;
+	m2-sata-en-gpios = 		<&aw9535_0  9 GPIO_ACTIVE_HIGH>;
+	sata-clk-en-gpios = 		<&aw9535_0 12 GPIO_ACTIVE_HIGH>;
+	sata-clk-pwren-gpios = 		<&aw9535_1 13 GPIO_ACTIVE_HIGH>;
+	status = "disabled";
+};

arch/riscv/boot/dts/zhihe/a210-evb-sec.dts

@@ -0,0 +1,2 @@
+#include "a210-evb.dts"
+#include "a210-sec-tee.dtsi"

arch/riscv/boot/dts/zhihe/a210-evb.dts

@@ -1290,7 +1290,7 @@
 				remote-endpoint = <&typec_con_usb>;
 			};
 		};
-	};	
+	};
 };
 
 &i2c5 {

arch/riscv/boot/dts/zhihe/a210-sec-tee.dtsi

@@ -0,0 +1,175 @@
+//sec-tee.dtsi
+
+/ {
+    //compatible = "zhihe,p100,tee";//update dst compatible value for tee
+    chosen {
+        opensbi-domains {
+            compatible = "opensbi,domain,config";
+            tmem0: tmem0 {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x20000000>;
+                order = <28>; // 256MiB tee device io
+            };
+            tmem1: tmem1 {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x30000000>;
+                order = <27>; // 128MiB tee device io
+            };
+            teeosmem: teeosmem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x88000000>;
+                order = <25>; // 32MiB, optee-os
+            };
+            teess_mem0: teess_mem0 {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x27500000>;
+                order = <19>; // 512KB, EIP+TEE_DMAC+TEE_OCRAM
+            };
+            teess_mem1: teess_mem1 {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x27410000>;
+                order = <12>; // 4KB, EFUSE
+            };
+            iopmp_vpmem: iopmp_vpmem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x27500000>;
+                order = <12>; // 4KB
+            };
+            iopmp_vimem: iopmp_vimem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x26372000>;
+                order = <12>; // 4KB
+            };
+            iopmp_npumem: iopmp_npumem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x27102000>;
+                order = <12>; // 4KB
+            };
+            iopmp_vomem: iopmp_vomem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x26712000>;
+                order = <12>; // 4KB
+            };
+            iopmp_peri1mem: iopmp_peri1mem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x22032000>;
+                order = <12>; // 4KB
+            };
+            iopmp_pciemem: iopmp_pciemem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x2A012000>;
+                order = <12>; // 4KB
+            };
+            iopmp_usbmem: iopmp_usbmem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x28022000>;
+                order = <12>; // 4KB
+            };
+            iopmp_gpumem: iopmp_gpumem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x26D12000>;
+                order = <12>; // 4KB
+            };
+            uart4mem: uart4mem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x08401000>;
+                order = <12>;
+                mmio;
+            };
+            plicmem: plicem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x18000000>;
+                order = <22>;
+                mmio;
+            };
+            reemem1: reemem1 {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x80000000>;
+                order = <27>; // 128MiB, linux-os, {0x80000000~0x87ffffff}
+            };
+            allmem: allmem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x0>;
+                order = <64>;
+            };
+            tdomain: tee-domain {
+                compatible = "opensbi,domain,instance";
+                regions =<&plicmem 0x1b>, <&uart4mem 0x1b>, <&allmem 0x38>;
+                possible-harts = <&c908_0 &c908_1 &c908_2 &c908_3 &c920_4 &c920_5 &c920_6 &c920_7>;
+                next-addr = <0x0 0x88000000>; /* optee_os: CFG_TDDRAM_START */
+                next-mode = <0x1>;
+                system-reset-allowed;
+                system-suspend-allowed;
+            };
+            udomain: ree-domain {
+                compatible = "opensbi,domain,instance";
+                regions = <&teeosmem 0x0>,
+                          <&teess_mem0 0x0>,
+                          <&teess_mem1 0x0>,
+                          <&plicmem 0x1b>,
+                          <&allmem 0x38>;
+                possible-harts = <&c908_0 &c908_1 &c908_2 &c908_3 &c920_4 &c920_5 &c920_6 &c920_7>;
+                boot-hart = <&c908_0>;
+                next-addr = <0x0 0x90000000>; /* u-boot: CONFIG_TEXT_BASE */
+                next-mode = <0x1>;
+                system-reset-allowed;
+                system-suspend-allowed;
+            };
+        };
+    };
+
+    firmware {
+        optee {
+            compatible = "linaro,optee-tz";
+            method = "smc";
+            memory-region = <&optee_shm>;
+        };
+    };
+
+    reserved-memory {
+        optee_shm: optee@8a000000 {
+            reg = <0x0 0x8a000000 0x0 0x02000000>;
+            no-map;
+        };
+    };
+};
+
+&eip_28 {
+    status = "disabled";
+};
+
+&nvmem_controller {
+    status = "disabled";
+};
+
+&c908_0 {
+    opensbi-domain = <&tdomain>;
+};
+
+&c908_1 {
+    opensbi-domain = <&udomain>;
+};
+
+&c908_2 {
+    opensbi-domain = <&udomain>;
+};
+
+&c908_3 {
+    opensbi-domain = <&udomain>;
+};
+
+&c920_4 {
+    opensbi-domain = <&udomain>;
+};
+
+&c920_5 {
+    opensbi-domain = <&udomain>;
+};
+
+&c920_6 {
+    opensbi-domain = <&udomain>;
+};
+
+&c920_7 {
+    opensbi-domain = <&udomain>;
+};

arch/riscv/boot/dts/zhihe/a210-soc-core.dtsi

@@ -564,7 +564,7 @@
 				 <&clk TOP_PERI_TDM_SRC_CLK_MUX>, <&clk TOP_PAD_SENSOR_VCLK0_DIV>,
 				 <&clk TOP_PAD_SENSOR_VCLK1_DIV>, <&clk TOP_PERI_HIRES_CLK0_DIV>,
 				 <&clk TOP_PERI_HIRES_CLK1_DIV>, <&clk TOP_TEE_CLK_DIV>,
-				 <&clk TOP_PERI_EMMC_REF_CLK_DIV>, <&clk TOP_PERI_MST_ACLK0_DIV>, 
+				 <&clk TOP_PERI_EMMC_REF_CLK_DIV>, <&clk TOP_PERI_MST_ACLK0_DIV>,
 				 <&clk TOP_PERI_MST_CLK1_DIV>;
 			clock-names = "peri0_timer_clk", "peri1_i2s0_src_clk", "peri2_i2s1_src_clk",
 				      "peri2_i2s2_src_clk", "peri2_i2s3_src_clk", "peri1_spi_ssi_clk",

arch/riscv/configs/a210_evb_defconfig

@@ -356,3 +356,6 @@ CONFIG_FTRACE_SYSCALLS=y
 CONFIG_BPF_KPROBE_OVERRIDE=y
 CONFIG_FUNCTION_ERROR_INJECTION=y
 # CONFIG_RUNTIME_TESTING_MENU is not set
+# Enable TEE
+CONFIG_TEE=y
+CONFIG_OPTEE=y

drivers/pci/controller/dwc/pcie-zh.c

@@ -74,7 +74,11 @@ struct p100_plat_pcie {
 	struct gpio_desc		*pcie_bat_en;
 	struct gpio_desc		*pcie_3v3_en;
 	struct gpio_desc		*pcie_12v_en;
-	struct gpio_desc		*pcie_clk_en;	
+	struct gpio_desc		*pcie_clk_en;
+	struct gpio_desc		*minipcie_1v5_pwren;
+	struct gpio_desc		*minipcie_3v3_pwren;
+	struct gpio_desc		*minipcie_perst;
+	struct gpio_desc		*pcie_clk_pwren;
 };
 
 struct p100_plat_pcie_of_data {
@@ -391,6 +395,49 @@ static int p100_plat_pcie_probe(struct platform_device *pdev)
 		if (p100_plat_pcie->pcie_clk_en)
 			gpiod_set_value(p100_plat_pcie->pcie_clk_en, 1);
 
+		p100_plat_pcie->minipcie_1v5_pwren = devm_gpiod_get_optional(&pdev->dev,
+								      "minipcie-1v5-pwren",
+								      GPIOD_OUT_LOW);
+		if (IS_ERR(p100_plat_pcie->minipcie_1v5_pwren)) {
+			dev_err(&pdev->dev, "Failed to get minipcie-1v5-pwren GPIO\n");
+			return PTR_ERR(p100_plat_pcie->minipcie_1v5_pwren);
+		}
+
+		if (p100_plat_pcie->minipcie_1v5_pwren)
+			gpiod_set_value(p100_plat_pcie->minipcie_1v5_pwren, 1);
+
+		p100_plat_pcie->minipcie_3v3_pwren = devm_gpiod_get_optional(&pdev->dev,
+								      "minipcie-3v3-pwren",
+								      GPIOD_OUT_LOW);
+		if (IS_ERR(p100_plat_pcie->minipcie_3v3_pwren)) {
+			dev_err(&pdev->dev, "Failed to get minipcie-3v3-pwren GPIO\n");
+			return PTR_ERR(p100_plat_pcie->minipcie_3v3_pwren);
+		}
+
+		if (p100_plat_pcie->minipcie_3v3_pwren)
+			gpiod_set_value(p100_plat_pcie->minipcie_3v3_pwren, 1);
+
+		p100_plat_pcie->minipcie_perst = devm_gpiod_get_optional(&pdev->dev,
+								      "minipcie-perst",
+								      GPIOD_OUT_LOW);
+		if (IS_ERR(p100_plat_pcie->minipcie_perst)) {
+			dev_err(&pdev->dev, "Failed to get minipcie-perst GPIO\n");
+			return PTR_ERR(p100_plat_pcie->minipcie_perst);
+		}
+
+		if (p100_plat_pcie->minipcie_perst)
+			gpiod_set_value(p100_plat_pcie->minipcie_perst, 1);
+
+		p100_plat_pcie->pcie_clk_pwren = devm_gpiod_get_optional(&pdev->dev,
+								      "pcie-clk-pwren",
+								      GPIOD_OUT_LOW);
+		if (IS_ERR(p100_plat_pcie->pcie_clk_pwren)) {
+			dev_err(&pdev->dev, "Failed to get pcie-clk-pwren GPIO\n");
+			return PTR_ERR(p100_plat_pcie->pcie_clk_pwren);
+		}
+
+		if (p100_plat_pcie->pcie_clk_pwren)
+			gpiod_set_value(p100_plat_pcie->pcie_clk_pwren, 1);
 		p100_plat_pcie->pci->dbi_base = p100_plat_pcie->apb_base;
 
 		ret = p100_plat_add_pcie_port(p100_plat_pcie, pdev);

drivers/tee/optee/smc_abi.c

@@ -33,6 +33,7 @@
 #define CREATE_TRACE_POINTS
 #include "optee_trace.h"
 #include <linux/suspend.h>
+#include <asm/sbi.h>
 
 /*
  * This file implement the SMC ABI used when communicating with secure world
@@ -59,6 +60,9 @@
 /* SMC ABI considers at most a single TEE firmware */
 static unsigned int pcpu_irq_num;
 
+/* MVENDERID register value*/
+static long crs_mvendorid;
+
 static int optee_cpuhp_enable_pcpu_irq(unsigned int cpu)
 {
 	enable_percpu_irq(pcpu_irq_num, IRQ_TYPE_NONE);
@@ -1434,6 +1438,7 @@ static void optee_riscv(unsigned long arg0, unsigned long arg1,
 		unsigned long arg6, unsigned long arg7,
 		struct arm_smccc_res *res)
 {
+	unsigned long ext = SBI_EXT_VENDOR_START + crs_mvendorid;
 	register uintptr_t a0 asm ("a0") = (uintptr_t)arg0;
 	register uintptr_t a1 asm ("a1") = (uintptr_t)arg1;
 	register uintptr_t a2 asm ("a2") = (uintptr_t)arg2;
@@ -1441,7 +1446,7 @@ static void optee_riscv(unsigned long arg0, unsigned long arg1,
 	register uintptr_t a4 asm ("a4") = (uintptr_t)arg4;
 	register uintptr_t a5 asm ("a5") = (uintptr_t)arg5;
 	register uintptr_t a6 asm ("a6") = (uintptr_t)arg6;
-	register uintptr_t a7 asm ("a7") = (uintptr_t)0x09000000;
+	register uintptr_t a7 asm ("a7") = (uintptr_t)ext;
 	register uintptr_t t0 asm ("t0") = (uintptr_t)arg7;
 
 	asm volatile ("ecall"
@@ -1654,6 +1659,8 @@ static int optee_probe(struct platform_device *pdev)
 	u32 sec_caps;
 	int rc;
 
+	crs_mvendorid = sbi_get_mvendorid();
+
 	invoke_fn = get_invoke_func(&pdev->dev);
 	if (IS_ERR(invoke_fn))
 		return PTR_ERR(invoke_fn);