USB3 and PCIE0 of k1x shares a combo phy. BIT(8) of APMU register APMU_PCIE_CLK_RES_CTRL_0 is designed for USB3 to reset the combo phy without resetting the PCIE0. Change-Id: I1935d228b1c4c8d81fd280a8dc245806539d7104 Signed-off-by: Junzhong Pan <junzhong.pan@spacemit.com>