c0e6859eb0
user manual: 1.config: enable MMC_SDHCI_OF_K1X_PANIC 2.config: CONFIG_PSTORE_BLK_BLKDEV,eg:/dev/mmcblk0p7 3.partiton:add pstore partiton test cmd: 1. mount -t pstore pstore /sys/fs/pstore 2. echo c > /proc/sysrq-trigger Change-Id: I88fbe8faedc5ccdffece72e2813e9d173dda9d65 Signed-off-by: lijuan <juan.li@spacemit.com>
421 lines
12 KiB
C
421 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Spacemit Mobile Storage Host Controller
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*
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* Copyright (C) 2023 Spacemit
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*/
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#ifndef __K1_MMC_PANIC_H__
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#define __K1_MMC_PANIC_H__
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/*
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* Controller registers
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*/
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
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#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA 0x01
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#define SDHCI_TRNS_BLK_CNT_EN 0x02
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#define SDHCI_TRNS_AUTO_CMD12 0x04
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#define SDHCI_TRNS_AUTO_CMD23 0x08
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#define SDHCI_TRNS_AUTO_SEL 0x0C
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#define SDHCI_TRNS_READ 0x10
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#define SDHCI_TRNS_MULTI 0x20
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_ABORTCMD 0xC0
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
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#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_CMD_INHIBIT 0x00000001
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#define SDHCI_DATA_INHIBIT 0x00000002
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#define SDHCI_DOING_WRITE 0x00000100
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#define SDHCI_DOING_READ 0x00000200
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#define SDHCI_SPACE_AVAILABLE 0x00000400
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#define SDHCI_DATA_AVAILABLE 0x00000800
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#define SDHCI_CARD_PRESENT 0x00010000
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#define SDHCI_CARD_PRES_SHIFT 16
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#define SDHCI_CD_STABLE 0x00020000
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#define SDHCI_CD_LVL 0x00040000
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#define SDHCI_CD_LVL_SHIFT 18
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#define SDHCI_WRITE_PROTECT 0x00080000
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#define SDHCI_DATA_LVL_MASK 0x00F00000
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#define SDHCI_DATA_LVL_SHIFT 20
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#define SDHCI_DATA_0_LVL_MASK 0x00100000
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#define SDHCI_CMD_LVL 0x01000000
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_CTRL_ADMA1 0x08
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#define SDHCI_CTRL_ADMA32 0x10
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#define SDHCI_CTRL_ADMA64 0x18
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#define SDHCI_CTRL_ADMA3 0x18
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#define SDHCI_CTRL_8BITBUS 0x20
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#define SDHCI_CTRL_CDTEST_INS 0x40
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#define SDHCI_CTRL_CDTEST_EN 0x80
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_180 0x0A
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#define SDHCI_POWER_300 0x0C
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#define SDHCI_POWER_330 0x0E
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/*
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* VDD2 - UHS2 or PCIe/NVMe
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* VDD2 power on/off and voltage select
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*/
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#define SDHCI_VDD2_POWER_ON 0x10
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#define SDHCI_VDD2_POWER_120 0x80
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#define SDHCI_VDD2_POWER_180 0xA0
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_WAKE_UP_CONTROL 0x2B
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#define SDHCI_WAKE_ON_INT 0x01
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#define SDHCI_WAKE_ON_INSERT 0x02
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#define SDHCI_WAKE_ON_REMOVE 0x04
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#define SDHCI_CLOCK_CONTROL 0x2C
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#define SDHCI_DIVIDER_SHIFT 8
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#define SDHCI_DIVIDER_HI_SHIFT 6
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#define SDHCI_DIV_MASK 0xFF
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#define SDHCI_DIV_MASK_LEN 8
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#define SDHCI_DIV_HI_MASK 0x300
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#define SDHCI_PROG_CLOCK_MODE 0x0020
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_PLL_EN 0x0008
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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#define SDHCI_TIMEOUT_CONTROL 0x2E
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_INT_RESPONSE 0x00000001
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#define SDHCI_INT_DATA_END 0x00000002
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#define SDHCI_INT_BLK_GAP 0x00000004
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#define SDHCI_INT_DMA_END 0x00000008
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#define SDHCI_INT_SPACE_AVAIL 0x00000010
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#define SDHCI_INT_DATA_AVAIL 0x00000020
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#define SDHCI_INT_CARD_INSERT 0x00000040
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#define SDHCI_INT_CARD_REMOVE 0x00000080
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#define SDHCI_INT_CARD_INT 0x00000100
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#define SDHCI_INT_RETUNE 0x00001000
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#define SDHCI_INT_CQE 0x00004000
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#define SDHCI_INT_ERROR 0x00008000
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#define SDHCI_INT_TIMEOUT 0x00010000
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#define SDHCI_INT_CRC 0x00020000
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#define SDHCI_INT_END_BIT 0x00040000
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#define SDHCI_INT_INDEX 0x00080000
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#define SDHCI_INT_DATA_TIMEOUT 0x00100000
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#define SDHCI_INT_DATA_CRC 0x00200000
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#define SDHCI_INT_DATA_END_BIT 0x00400000
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#define SDHCI_INT_BUS_POWER 0x00800000
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#define SDHCI_INT_AUTO_CMD_ERR 0x01000000
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#define SDHCI_INT_ADMA_ERROR 0x02000000
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#define SDHCI_INT_TUNING_ERROR 0x04000000
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#define SDHCI_INT_NORMAL_MASK 0x00007FFF
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#define SDHCI_INT_ERROR_MASK 0xFFFF8000
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#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
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SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
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SDHCI_INT_AUTO_CMD_ERR)
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#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
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SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
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SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
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SDHCI_INT_BLK_GAP | SDHCI_INT_TUNING_ERROR)
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#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
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#define SDHCI_CQE_INT_ERR_MASK ( \
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SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
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SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
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SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
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#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
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#define SDHCI_AUTO_CMD_STATUS 0x3C
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#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
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#define SDHCI_AUTO_CMD_CRC 0x00000004
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#define SDHCI_AUTO_CMD_END_BIT 0x00000008
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#define SDHCI_AUTO_CMD_INDEX 0x00000010
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#define SDHCI_HOST_CONTROL2 0x3E
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#define SDHCI_CTRL_UHS_MASK 0x0007
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#define SDHCI_CTRL_UHS_SDR12 0x0000
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#define SDHCI_CTRL_UHS_SDR25 0x0001
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#define SDHCI_CTRL_UHS_SDR50 0x0002
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#define SDHCI_CTRL_UHS_SDR104 0x0003
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#define SDHCI_CTRL_UHS_DDR50 0x0004
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#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
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#define SDHCI_CTRL_VDD_180 0x0008
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#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
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#define SDHCI_CTRL_DRV_TYPE_B 0x0000
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#define SDHCI_CTRL_DRV_TYPE_A 0x0010
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#define SDHCI_CTRL_DRV_TYPE_C 0x0020
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#define SDHCI_CTRL_DRV_TYPE_D 0x0030
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#define SDHCI_CTRL_EXEC_TUNING 0x0040
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#define SDHCI_CTRL_TUNED_CLK 0x0080
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#define SDHCI_CMD23_ENABLE 0x0800
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#define SDHCI_CTRL_V4_MODE 0x1000
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#define SDHCI_CTRL_64BIT_ADDR 0x2000
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#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0)
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8)
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8)
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_CAN_DO_8BIT 0x00040000
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#define SDHCI_CAN_DO_ADMA2 0x00080000
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#define SDHCI_CAN_DO_ADMA1 0x00100000
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#define SDHCI_CAN_DO_HISPD 0x00200000
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#define SDHCI_CAN_DO_SDMA 0x00400000
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#define SDHCI_CAN_DO_SUSPEND 0x00800000
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#define SDHCI_CAN_VDD_330 0x01000000
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#define SDHCI_CAN_VDD_300 0x02000000
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#define SDHCI_CAN_VDD_180 0x04000000
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#define SDHCI_CAN_64BIT_V4 0x08000000
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#define SDHCI_CAN_64BIT 0x10000000
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#define SDHCI_CAPABILITIES_1 0x44
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#define SDHCI_SUPPORT_SDR50 0x00000001
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#define SDHCI_SUPPORT_SDR104 0x00000002
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#define SDHCI_SUPPORT_DDR50 0x00000004
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#define SDHCI_DRIVER_TYPE_A 0x00000010
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#define SDHCI_DRIVER_TYPE_C 0x00000020
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#define SDHCI_DRIVER_TYPE_D 0x00000040
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#define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8)
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#define SDHCI_USE_SDR50_TUNING 0x00002000
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#define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14)
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#define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16)
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#define SDHCI_CAN_DO_ADMA3 0x08000000
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#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
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#define SDHCI_MAX_CURRENT 0x48
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#define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0)
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#define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0)
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#define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8)
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#define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16)
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#define SDHCI_MAX_CURRENT_MULTIPLIER 4
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/* 4C-4F reserved for more max current */
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#define SDHCI_SET_ACMD12_ERROR 0x50
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#define SDHCI_SET_INT_ERROR 0x52
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#define SDHCI_ADMA_ERROR 0x54
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/* 55-57 reserved */
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#define SDHCI_ADMA_ADDRESS 0x58
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#define SDHCI_ADMA_ADDRESS_HI 0x5C
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/* 60-FB reserved */
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#define SDHCI_PRESET_FOR_HIGH_SPEED 0x64
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#define SDHCI_PRESET_FOR_SDR12 0x66
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#define SDHCI_PRESET_FOR_SDR25 0x68
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#define SDHCI_PRESET_FOR_SDR50 0x6A
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#define SDHCI_PRESET_FOR_SDR104 0x6C
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#define SDHCI_PRESET_FOR_DDR50 0x6E
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#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
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#define SDHCI_PRESET_DRV_MASK GENMASK(15, 14)
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#define SDHCI_PRESET_CLKGEN_SEL BIT(10)
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#define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_VERSION 0xFE
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#define SDHCI_VENDOR_VER_MASK 0xFF00
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#define SDHCI_VENDOR_VER_SHIFT 8
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#define SDHCI_SPEC_VER_MASK 0x00FF
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#define SDHCI_SPEC_VER_SHIFT 0
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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#define SDHCI_SPEC_400 3
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#define SDHCI_SPEC_410 4
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#define SDHCI_SPEC_420 5
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/*
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* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
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*/
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#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
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#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
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/*
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* End of controller registers.
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*/
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#define MMC_DATA_READ 1
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#define MMC_DATA_WRITE 2
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#define MMC_CMD_GO_IDLE_STATE 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RELATIVE_ADDR 3
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#define MMC_CMD_SET_DSR 4
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_EXT_CSD 8
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_STOP_TRANSMISSION 12
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_SINGLE_BLOCK 17
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define MMC_CMD_SEND_TUNING_BLOCK 19
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#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
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#define MMC_CMD_SET_BLOCK_COUNT 23
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#define MMC_CMD_WRITE_SINGLE_BLOCK 24
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#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
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#define MMC_CMD_ERASE_GROUP_START 35
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#define MMC_CMD_ERASE_GROUP_END 36
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#define MMC_CMD_ERASE 38
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#define MMC_CMD_APP_CMD 55
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#define MMC_CMD_SPI_READ_OCR 58
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#define MMC_CMD_SPI_CRC_ON_OFF 59
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#define MMC_CMD_RES_MAN 62
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#define MMC_CMD62_ARG1 0xefac62ec
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#define MMC_CMD62_ARG2 0xcbaea7
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#define SD_CMD_SEND_RELATIVE_ADDR 3
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#define SD_CMD_SWITCH_FUNC 6
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#define SD_CMD_SEND_IF_COND 8
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#define SD_CMD_SWITCH_UHS18V 11
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#define SD_CMD_APP_SET_BUS_WIDTH 6
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#define SD_CMD_APP_SD_STATUS 13
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#define SD_CMD_ERASE_WR_BLK_START 32
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#define SD_CMD_ERASE_WR_BLK_END 33
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#define SD_CMD_APP_SEND_OP_COND 41
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#define SD_CMD_APP_SEND_SCR 51
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#define MMC_RSP_PRESENT (1 << 0)
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#define MMC_RSP_136 (1 << 1) /* 136 bit response */
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#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
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#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
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#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
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#define MMC_RSP_NONE (0)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
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MMC_RSP_BUSY)
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#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
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#define MMC_RSP_R3 (MMC_RSP_PRESENT)
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#define MMC_RSP_R4 (MMC_RSP_PRESENT)
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#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_STATUS_MASK (~0x0206BF7F)
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#define MMC_STATUS_SWITCH_ERROR (1 << 7)
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#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
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#define MMC_STATUS_CURR_STATE (0xf << 9)
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#define MMC_STATUS_ERROR (1 << 19)
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#define MMC_STATE_PRG (7 << 9)
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#define MMC_STATE_TRANS (4 << 9)
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#define MMC_BLOCK_SIZE 512
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#define MMC_MAX_BLK_COUNT 65535
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struct mmc_cmd {
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unsigned short cmdidx;
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unsigned int resp_type;
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unsigned int cmdarg;
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unsigned int response[4];
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};
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struct mmc_data {
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union {
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char *dest;
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const char *src; /* src buffers don't get written to */
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};
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unsigned int flags;
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unsigned int blocks;
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unsigned int blocksize;
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};
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static inline void sdhci_writel(char *host, unsigned int val, int reg)
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{
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writel(val, host + reg);
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}
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static inline void sdhci_writew(char *host, unsigned short val, int reg)
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{
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writew(val, host + reg);
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}
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static inline void sdhci_writeb(char *host, unsigned char val, int reg)
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{
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writeb(val, host + reg);
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}
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static inline unsigned int sdhci_readl(char *host, int reg)
|
|
{
|
|
return readl(host + reg);
|
|
}
|
|
|
|
static inline unsigned short sdhci_readw(char *host, int reg)
|
|
{
|
|
return readw(host + reg);
|
|
}
|
|
|
|
static inline unsigned char sdhci_readb(char *host, int reg)
|
|
{
|
|
return readb(host + reg);
|
|
}
|
|
|
|
ssize_t
|
|
k1_mmc_panic_rtest(struct device *dev, struct device_attribute *attr, char *buf);
|
|
ssize_t
|
|
k1_mmc_pancic_wrtest(struct device *dev, struct device_attribute *attr,
|
|
const char *buf, size_t count);
|
|
int k1_mmc_panic_init_ps(void *data);
|
|
#endif
|