8151a6dbbc
Change-Id: I3f5cec193f5796c05a415eb413bc0093d9f6eaf4 Signed-off-by: wanlong <long.wan@spacemit.com>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* include/linux/platform_data/k1x_sdhci.h
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*
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* Copyright (C) 2023 Spacemit
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _K1X_SDHCI_H_
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#define _K1X_SDHCI_H_
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#define CANDIDATE_WIN_NUM 3
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#define SELECT_DELAY_NUM 9
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#define WINDOW_1ST 0
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#define WINDOW_2ND 1
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#define WINDOW_3RD 2
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#define RX_TUNING_WINDOW_THRESHOLD 80
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#define RX_TUNING_DLINE_REG 0x09
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#define TX_TUNING_DLINE_REG 0x00
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#define TX_TUNING_DELAYCODE 127
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enum window_type {
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LEFT_WINDOW = 0,
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MIDDLE_WINDOW = 1,
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RIGHT_WINDOW = 2,
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};
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struct tuning_window {
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u8 type;
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u8 min_delay;
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u8 max_delay;
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};
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struct rx_tuning {
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u8 rx_dline_reg;
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u8 select_delay_num;
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u8 current_delay_index;
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/* 0: biggest window, 1: bigger, 2: small */
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struct tuning_window windows[CANDIDATE_WIN_NUM];
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u8 select_delay[SELECT_DELAY_NUM];
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u32 card_cid[4];
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u8 window_limit;
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u8 tuning_fail;
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u8 window_type;
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};
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/*
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* struct k1x_sdhci_platdata() - Platform device data for Spacemit K1x SDHCI
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* @flags: flags for platform requirement
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* @host_caps: Standard MMC host capabilities bit field
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* @host_caps2: Standard MMC host capabilities bit field
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* @host_caps_disable: Aquila MMC host capabilities disable bit field
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* @host_caps2_disable: Aquila MMC host capabilities disable bit field
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* @quirks: quirks of platform
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* @quirks2: quirks2 of platform
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* @pm_caps: pm_caps of platform
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*/
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struct k1x_sdhci_platdata {
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u32 host_freq;
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u32 flags;
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u32 host_caps;
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u32 host_caps2;
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u32 host_caps_disable;
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u32 host_caps2_disable;
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u32 quirks;
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u32 quirks2;
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u32 pm_caps;
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u32 aib_mmc1_io_reg;
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u32 apbc_asfar_reg;
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u32 apbc_assar_reg;
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u8 tx_dline_reg;
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u8 tx_delaycode;
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u8 tx_delaycode_cnt;
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u32 tx_delaycode_array[2];
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bool tx_need_update;
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wait_queue_head_t wait_queue;
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atomic_t ref_count;
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u8 phy_driver_sel;
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struct rx_tuning rxtuning;
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u8 need_reset_dllcfg1;
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u32 prev_dllcfg1;
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u32 curr_dllcfg1;
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u32 new_dllcfg1;
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u8 dllcfg1_odd_reset;
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u32 rx_tuning_freq;
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};
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#endif /* _K1X_SDHCI_H_ */
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