e9e49ad9ee
1. dw_apb_timer: revert the change-id:I586ebcec8e3b03cec44a1845b1bee36b79c14d0e and add a spinlock
in funcion: apbt_next_event & dw_apb_clockevent_irq
2. irq-sifive-plic: Modify the basic address offset and size to fit the SPACEMIT plat
3. irq-sifive-plic: when performing irq binding operations, it is best
to write down the sclaim register
Change-Id: Id13e5e17384726183fd98d232b5edfab838f6134
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* (C) Copyright 2009 Intel Corporation
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* Author: Jacob Pan (jacob.jun.pan@intel.com)
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*
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* Shared with ARM platforms, Jamie Iles, Picochip 2011
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*
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* Support for the Synopsys DesignWare APB Timers.
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*/
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#ifndef __DW_APB_TIMER_H__
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#define __DW_APB_TIMER_H__
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#define APBTMRS_REG_SIZE 0x14
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struct dw_apb_timer {
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void __iomem *base;
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unsigned long freq;
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int irq;
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};
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struct dw_apb_clock_event_device {
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struct clock_event_device ced;
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struct dw_apb_timer timer;
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void (*eoi)(struct dw_apb_timer *);
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raw_spinlock_t timer_lock;
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};
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struct dw_apb_clocksource {
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struct dw_apb_timer timer;
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struct clocksource cs;
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};
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void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced);
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void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced);
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void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced);
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void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced);
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struct dw_apb_clock_event_device *
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dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
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void __iomem *base, int irq, unsigned long freq);
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struct dw_apb_clocksource *
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dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
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unsigned long freq);
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void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs);
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void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
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u64 dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
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#endif /* __DW_APB_TIMER_H__ */
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