Merge tag 'amd-drm-next-6.3-2023-01-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.3-2023-01-06: amdgpu: - secure display support for multiple displays - DML optimizations - DCN 3.2 updates - PSR updates - DP 2.1 updates - SR-IOV RAS updates - VCN RAS support - SMU 13.x updates - Switch 1 element arrays to flexible arrays - Add RAS support for DF 4.3 - Stack size improvements - S0ix rework - Soft reset fix - Allow 0 as a vram limit on APUs - Display fixes - Misc code cleanups - Documentation fixes - Handle profiling modes for SMU13.x amdkfd: - Error handling fixes - PASID fixes radeon: - Switch 1 element arrays to flexible arrays drm: - Add DP adaptive sync DPCD definitions UAPI: - Add new INFO queries for peak and min sclk/mclk for profile modes on newer chips Proposed mesa patch: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/278 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230106222037.7870-1-alexander.deucher@amd.com
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@@ -1679,10 +1679,10 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
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/* reserve vram for mem train according to TMR location */
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amdgpu_ttm_training_data_block_init(adev);
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ret = amdgpu_bo_create_kernel_at(adev,
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ctx->c2p_train_data_offset,
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ctx->train_data_size,
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&ctx->c2p_bo,
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NULL);
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ctx->c2p_train_data_offset,
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ctx->train_data_size,
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&ctx->c2p_bo,
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NULL);
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if (ret) {
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DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
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amdgpu_ttm_training_reserve_vram_fini(adev);
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@@ -1692,10 +1692,10 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
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}
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ret = amdgpu_bo_create_kernel_at(adev,
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adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
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adev->mman.discovery_tmr_size,
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&adev->mman.discovery_memory,
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NULL);
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adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
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adev->mman.discovery_tmr_size,
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&adev->mman.discovery_memory,
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NULL);
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if (ret) {
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DRM_ERROR("alloc tmr failed(%d)!\n", ret);
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amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
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@@ -1718,7 +1718,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
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{
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uint64_t gtt_size;
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int r;
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u64 vis_vram_limit;
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mutex_init(&adev->mman.gtt_window_lock);
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@@ -1741,12 +1740,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
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return r;
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}
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/* Reduce size of CPU-visible VRAM if requested */
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vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
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if (amdgpu_vis_vram_limit > 0 &&
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vis_vram_limit <= adev->gmc.visible_vram_size)
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adev->gmc.visible_vram_size = vis_vram_limit;
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/* Change the size here instead of the init above so only lpfn is affected */
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amdgpu_ttm_set_buffer_funcs_status(adev, false);
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#ifdef CONFIG_64BIT
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