From Stephen Warren:
ARM: tegra: single-zImage preparation work
Various cleanups and enhancements are made to core Tegra code towards the
aim of including Tegra in a multi-platform ARM kernel:
RTC, timer, and TWD are configured via device tree.
SPARSE_IRQ is enabled.
Tegra's debug_ll options are simplified, and the macros brought into
line with other multi-platform implementations, and moved to the new
common location.
Two headers still need to be eliminated in order to include Tegra in a
multi-platform kernel/ <mach/{clk,powergate}.h>. A new common API needs
to be invented to replace parts of clk.h. powergate.h might be replaced
by regulators; this needs more investigation.
This pull request is based on tegra-for-3.8-dt, followed by a merge of
arm-soc's devel/debug_ll_init branch.
* tag 'tegra-for-3.8-single-zimage' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (58 commits)
ARM: tegra: move debug-macro.S to include/debug
ARM: tegra: don't include iomap.h from debug-macro.S
ARM: tegra: decouple uncompress.h and debug-macro.S
ARM: tegra: simplify DEBUG_LL UART selection options
ARM: tegra: select SPARSE_IRQ
ARM: tegra: enhance timer.c to get IO address from device tree
ARM: tegra: enhance timer.c to get IRQ info from device tree
ARM: timer: fix checkpatch warnings
ARM: tegra: add TWD to device tree
ARM: tegra: define DT bindings for and instantiate RTC
ARM: tegra: define DT bindings for and instantiate timer
ARM: tegra: whistler: enable HDMI port
ARM: tegra: tec: Enable HDMI output
ARM: tegra: plutux: Enable HDMI output
ARM: tegra: tamonten: Add host1x support
ARM: tegra: trimslice: enable HDMI port
ARM: tegra: harmony: enable HDMI port
ARM: tegra: Add Tegra30 host1x support
ARM: tegra: Add Tegra20 host1x support
ARM: tegra: trimslice: enable SPI flash
...
From Stephen Warren:
ARM: tegra: device tree changes
A wide variety of device tree additions are made across many Tegra
boards:
* WiFi is supported on Seaboard, Ventana, and Cardhu.
* An I2C mux is added for Ventana, and Tamonten.
* SPI flash is added to Cardhu, and TrimSlice.
* Temperature sensors are added to Harmony, Tamonten, and Ventana.
* host1x (graphics/display controller) is added to the SoC include files.
* HDMI displays are enabled on Harmony, TrimSlice, Tamonten, Plutux, Tec,
and Whistler.
This pull request is based on tegra-for-3.8-soc.
* tag 'tegra-for-3.8-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (47 commits)
ARM: tegra: whistler: enable HDMI port
ARM: tegra: tec: Enable HDMI output
ARM: tegra: plutux: Enable HDMI output
ARM: tegra: tamonten: Add host1x support
ARM: tegra: trimslice: enable HDMI port
ARM: tegra: harmony: enable HDMI port
ARM: tegra: Add Tegra30 host1x support
ARM: tegra: Add Tegra20 host1x support
ARM: tegra: trimslice: enable SPI flash
ARM: tegra: dts: add sflash controller dt entry
ARM: tegra: ventana: Add NCT1008 temperature sensor
ARM: tegra: tamonten: Add NCT1008 temperature sensor
ARM: tegra: harmony: Add ADT7641 temperature sensor
ARM: tegra: tec: Remove redundant DT properties
ARM: tegra: tamonten: Add DDC/PTA pinmux
ARM: tegra: dts: cardhu: enable SLINK4
ARM: tegra: dts: add slink controller dt entry
ARM: dt: tegra: ventana: define pinmux for ddc
ARM: dt: t30 cardhu: set pinmux and power for wlan
ARM: dt: t20 ventana: set pinmux and power for wlan
...
From Stephen Warren:
ARM: tegra: cleanup for 3.8
Various trivial cleanup changes of the Tegra code for 3.8.
Many of the changes simply remove useless #include statements, which
enable those headers to be removed or moved later, as work towards
multi-platform zImage support.
<mach/{iram,io}map.h> are moved up to arch/arm/mach-tegra to prevent
any new code outside mach-tegra from using them.
Finally, the regulator definitions in all board device tree files are
updated to use the new simpler syntax that was agreed upon.
* tag 'tegra-for-3.8-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: move irammap.h to mach-tegra
ARM: tegra: move iomap.h to mach-tegra
ARM: tegra: remove <mach/dma.h>
ARM: tegra: move tegra-ahb.h out of arch/arm/mach-tegra/
ARM: tegra: remove unnecessary includes of <mach/*.h>
iommu: tegra: remove include of <mach/iomap.h>
staging: nvec: remove include of <mach/iomap.h>
crypto: tegra: remove include of <mach/clk.h>
ARM: tegra: update *.dts for regulator-compatible deprecation
usb: phy: tegra remove include of <mach/iomap.h>
usb: host: tegra remove include of <mach/iomap.h>
In Marvell PXA/MMP silicons, input schmitt disable value is 0x40, not 0.
So append new config parameter -- input schmitt disable.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Let's stop spawning the pinctrl driver from the GPIO driver,
we have these two mechanisms broken apart now, and they can
each probe in isolation. If the GPIO driver cannot find its
pin controller (pinctrl-u300), the pin controller core will
tell it to defer probing.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a function to the pinctrl core to retrieve the GPIO
range associated with a certain pin for a certain controller.
This is needed when a pinctrl driver want to look up the
corresponding struct gpio_chip for a certain pin. As the
GPIO drivers can now create these ranges themselves, the
pinctrl driver no longer knows about all its associated GPIO
chips.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rename the function find_pinctrl_and_add_gpio_range()
to pinctrl_find_and_add_gpio_range() so as to be consistent
with the rest of the functions.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Like with commit 3c739ad0df
it is not always enough to specify all the pins of a gpio_chip
from offset zero to be added to a pin map range, since the
mapping from GPIO to pin controller may not be linear at all,
but need to be broken into a few consecutive sub-ranges or
1-pin entries for complicated cases. The ranges may also be
sparse.
This alters the signature of the function to accept offsets
into both the GPIO-chip local pinspace and the pin controller
local pinspace.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
From Nicolas Ferre:
One fix related to UART for the "headers move" branch
* tag 'at91-header' of git://github.com/at91linux/linux-at91:
atmel: move ATMEL_MAX_UART to platform_data/atmel.h
From Maxime Ripard:
Allwinner SoC support for 3.8
* tag 'tags/sunxi-support-for-3.8' of git://github.com/mripard/linux:
ARM: sunxi: Add entry to MAINTAINERS
ARM: sunxi: Add device tree for the A13 and the Olinuxino board
ARM: sunxi: Add earlyprintk support
ARM: sunxi: Add basic support for Allwinner A1x SoCs
irqchip: sunxi: Add irq controller driver
clocksource: sunxi: Add Allwinner A1X Timer Driver
clk: sunxi: Add dummy fixed rate clock for Allwinner A1X SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
The following pattern of code is tempting:
for_each_matching_node(np, table) {
match = of_match_node(table, np);
However, this results in iterating over table twice; the second time
inside of_match_node(). The implementation of for_each_matching_node()
already found the match, so this is redundant. Invent new function
of_find_matching_node_and_match() and macro
for_each_matching_node_and_match() to remove the double iteration,
thus transforming the above code to:
for_each_matching_node_and_match(np, table, &match)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Many of the regmap enabled drivers implementing one or more of the
readable, writeable, volatile and precious methods use the same code
pattern:
return ((reg >= X && reg <= Y) || (reg >= W && reg <= Z) || ...)
Switch to a data driven approach, using tables to describe
readable/writeable/volatile and precious registers ranges instead.
The table based check can still be overridden by passing the usual function
pointers via struct regmap_config.
Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The current platform device creation and registration code in
acpi_create_platform_device() is quite convoluted. This function
takes an ACPI device node as an argument and eventually calls
platform_device_register_resndata() to create and register a
platform device object on the basis of the information contained
in that code. However, it doesn't associate the new platform
device with the ACPI node directly, but instead it relies on
acpi_platform_notify(), called from within device_add(), to find
that ACPI node again with the help of acpi_platform_find_device()
and acpi_platform_match() and then attach the new platform device
to it. This causes an additional ACPI namespace walk to happen and
is clearly suboptimal.
Use the observation that it is now possible to initialize the ACPI
handle of a device before calling device_add() for it to make this
code more straightforward. Namely, add a new field to struct
platform_device_info allowing us to pass the ACPI handle of interest
to platform_device_register_full(), which will then use it to
initialize the new device's ACPI handle before registering it.
This will cause acpi_platform_notify() to use the ACPI handle from
the device structure directly instead of using the .find_device()
routine provided by the device's bus type. In consequence,
acpi_platform_bus, acpi_platform_find_device(), and
acpi_platform_match() are not necessary any more, so remove them.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To avoid adding an ACPI handle pointer to struct device on
architectures that don't use ACPI, or generally when CONFIG_ACPI is
not set, in which cases that pointer is useless, define struct
acpi_dev_node that will contain the handle pointer if CONFIG_ACPI is
set and will be empty otherwise and use it to represent the ACPI
device node field in struct device.
In addition to that define macros for reading and setting the ACPI
handle of a device that don't generate code when CONFIG_ACPI is
unset. Modify the ACPI subsystem to use those macros instead of
referring to the given device's ACPI handle directly.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch adds support for the ADIS16375, ADIS16480, ADIS16485, ADIS16488 6
degree to 10 degree of freedom IMUs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Factor out the code for parsing fixed point numbers into its own function and
make this function globally available. This allows us to reuse the code to parse
fixed point numbers in individual IIO drivers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This patch adds support for a new IIO channel type for pressure measurements.
This can for example be used for barometric pressure sensors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Some of the newer generation devices from the ADIS16XXX series have more
registers than what can be supported with the current register addressing
scheme. These devices implement register paging to support a larger register
range. Each page is 128 registers large and the currently active page can be
selected via register 0x00 in each page. This patch implements transparent
paging inside the common adis library. The register read/write interface stays
the same and when a register is accessed the library automatically switches to
the correct page if it is not already selected. The page number is encoded in
the upper bits of the register number, e.g. register 0x5 of page 1 is 0x85.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Some of the newer generation devices from the ADIS16XXX family have 32bit wide
register which spans two 16bit wide registers. This patch adds support for
reading and writing a 32bit wide register.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Provide a IIO debugfs register access function for the ADIS library. This
function can be used by individual drivers to allow raw register access via
debugfs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Looks like the iommu framework does not have generic functions
exported for all the needs yet. The hardware specific functions
are defined in files like intel-iommu.h and amd-iommu.h. Follow
the same standard for omap-iommu.h.
This is needed because we are removing plat and mach includes
for ARM common zImage support. Further work should continue
in the iommu framework context as only pure platform data will
be communicated from arch/arm/*omap*/* code to the iommu
framework.
Cc: Ido Yariv <ido@wizery.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Omar Ramirez Luna <omar.luna@linaro.org>
Cc: linux-media@vger.kernel.org
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Joerg Roedel <joro@8bytes.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The pool_size is always PAGE_SIZE, and since it is a software
configuration paramter (and not a hardware description parameter), we
cannot make it part of the Device Tree binding, so we'd better remove
it from the platform_data as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
There is no need for the platform_data to give this ID, it is simply
the channel number, so we can compute it inside the driver when
registering the channels.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Since we got rid of the per-XOR channel 'mv_xor' driver, now the
per-XOR engine driver that used to be called 'mv_xor_shared' can
simply be named 'mv_xor'.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
'struct mv_xor_shared_platform_data' used to be the platform_data
structure for the 'mv_xor_shared', but this driver is going to be
renamed simply 'mv_xor', so also rename its platform_data structure
accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
mv_xor_platform_data used to be the platform_data structure associated
to the 'mv_xor' driver. This driver no longer exists, and this data
structure really contains the properties of each XOR channel part of a
given XOR engine. Therefore 'struct mv_xor_channel_data' is a more
appropriate name.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Now that XOR channels are directly registered by the main
'mv_xor_shared' device ->probe() function and all users of the
'mv_xor' device have been removed, we can get rid of the latter.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Extend the XOR engine driver (currently called "mv_xor_shared") so
that XOR channels can be passed in the platform_data structure, and be
registered from there.
This will allow the users of the driver to be converted to the single
platform_driver variant of the mv_xor driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
'guarantee' is already removed from cgroup_task_migrate, so remove
the corresponding comments. Some other typos in cgroup are also
changed.
Cc: Tejun Heo <tj@kernel.org>
Cc: Li Zefan <lizefan@huawei.com>
Signed-off-by: Tao Ma <boyu.mt@taobao.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.
Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
Assign a unique proc inode to each namespace, and use that
inode number to ensure we only allocate at most one proc
inode for every namespace in proc.
A single proc inode per namespace allows userspace to test
to see if two processes are in the same namespace.
This has been a long requested feature and only blocked because
a naive implementation would put the id in a global space and
would ultimately require having a namespace for the names of
namespaces, making migration and certain virtualization tricks
impossible.
We still don't have per superblock inode numbers for proc, which
appears necessary for application unaware checkpoint/restart and
migrations (if the application is using namespace file descriptors)
but that is now allowd by the design if it becomes important.
I have preallocated the ipc and uts initial proc inode numbers so
their structures can be statically initialized.
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Generalize the proc inode allocation so that it can be
used without having to having to create a proc_dir_entry.
This will allow namespace file descriptors to remain light
weight entitities but still have the same inode number
when the backing namespace is the same.
Acked-by: Serge E. Hallyn <serge.hallyn@ubuntu.com>
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
- Add CLONE_THREAD to the unshare flags if CLONE_NEWUSER is selected
As changing user namespaces is only valid if all there is only
a single thread.
- Restore the code to add CLONE_VM if CLONE_THREAD is selected and
the code to addCLONE_SIGHAND if CLONE_VM is selected.
Making the constraints in the code clear.
Acked-by: Serge Hallyn <serge.hallyn@canonical.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
This allows entering a user namespace, and the ability
to store a reference to a user namespace with a bind
mount.
Addition of missing userns_ns_put in userns_install
from Gao feng <gaofeng@cn.fujitsu.com>
Acked-by: Serge Hallyn <serge.hallyn@canonical.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
The task_user_ns function hides the fact that it is getting the user
namespace from struct cred on the task. struct cred may go away as
soon as the rcu lock is released. This leads to a race where we
can dereference a stale user namespace pointer.
To make it obvious a struct cred is involved kill task_user_ns.
To kill the race modify the users of task_user_ns to only
reference the user namespace while the rcu lock is held.
Cc: Kees Cook <keescook@chromium.org>
Cc: James Morris <james.l.morris@oracle.com>
Acked-by: Kees Cook <keescook@chromium.org>
Acked-by: Serge Hallyn <serge.hallyn@canonical.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
Modify create_new_namespaces to explicitly take a user namespace
parameter, instead of implicitly through the task_struct.
This allows an implementation of unshare(CLONE_NEWUSER) where
the new user namespace is not stored onto the current task_struct
until after all of the namespaces are created.
Acked-by: Serge Hallyn <serge.hallyn@canonical.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
These are required for the clock infrastructure code to properly configure
and control the sta2x11 PLLs.
Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com>
Acked-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Since there are now many sta2x11-mfd platform devices, using defines
for their names looks like a better solution.
Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com>
Acked-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
A couple of predefined clocks (mux and gated) need to be
initialized with the virtual address of the clock's controlling
register and the address of a spinlock used to protect against
races.
This function exports such data for all the mfd cells.
Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com>
Acked-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
A driver for the apb-soc registers is needed by the clock
infrastructure code to configure and control clocks on the sta2x11
chip.
Since some of the functions in sta2x11-mfd.c were almost identical
for the two existing platform devices, the following changes
have been performed to avoid further code duplication while
adding the apb-soc-regs driver:
* The sctl_regs and apbreg_regs fields in struct sta2x11_mfd
have been turned into just one array of pointers accessed by
device index.
* Platform probe methods have become one-liners invoking a
common probe with the device's index as second parameter.
* For loops have been inserted where the same operations
were performed for each of the two bars of a pci device.
* The apbreg_mask and sctl_mask functions were almost identical,
so they were turned into inline functions invoking a common
__sta2x11_mfd_mask() with the platform device's index as last
parameter. To do this, enum sta2x11_mfd_plat_dev has been declared in
sta2x11-mfd.h and more device types have been added to it.
Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Davide Ciminaghi <ciminaghi@gnudd.com>
Acked-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This adds the mfd cell to use the i2c part of the Nano River Technologies
viperboard as i2c master.
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Olof Johansson