Prabhakar Kushwaha e982746844 powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2 ...

CHASSIS2 architecture never defines type of L2 cache present in SoC.
 it is dependent upon the core present in the SoC.
 for example,
    - e6500 core has L2 cluster (Kibo)
    - e5500 core has Backside L2 Cache

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

2013-10-16 16:13:11 -07:00

..

arm

Coding Style cleanup: drop some excessive empty lines

2013-10-14 16:06:54 -04:00

avr32

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24 09:44:38 -04:00

blackfin

Coding Style cleanup: replace leading SPACEs by TABs

2013-10-14 16:06:54 -04:00

m68k

Coding Style cleanup: replace leading SPACEs by TABs

2013-10-14 16:06:54 -04:00

microblaze

microblaze: Fix watchdog initialization

2013-10-16 09:24:38 -04:00

mips

Coding Style cleanup: remove trailing white space

2013-10-14 16:06:53 -04:00

nds32

nds32: introduce DMA allocation API

2013-08-09 01:51:11 +08:00

nios2

Coding Style cleanup: replace leading SPACEs by TABs

2013-10-14 16:06:54 -04:00

openrisc

Coding Style cleanup: replace leading SPACEs by TABs

2013-10-14 16:06:54 -04:00

powerpc

powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2

2013-10-16 16:13:11 -07:00

sandbox

Coding Style cleanup: remove trailing white space

2013-10-14 16:06:53 -04:00

sh

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24 09:44:38 -04:00

sparc

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24 09:44:38 -04:00

x86

Coding Style cleanup: remove trailing white space

2013-10-14 16:06:53 -04:00

.gitignore

update include/asm/ gitignore after move

2010-05-07 00:17:30 +02:00