forked from OERV-BSP/u-boot
f30539b8c4
Jaguar has an M.2 M-KEY slot for NVMes, connected to the PCIe3 4-lane PHY on RK3588. CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y is technically not necessary since it's required only for the M.2 E-KEY slot on the main PCB, but that is used typically for WiFi+BT modules, or on the mezzanine connector but the features exposed behind that connector aren't supported in U-Boot (no DT for it right now). However, if the PHY driver is missing, we get the following error message: pcie_dw_rockchip pcie@fe170000: failed to get pcie phy (ret=-19) and you would need to know which PCIe controller that is before deciding to ignore it. While after enabling the PHY driver, we are greeted with: pcie_dw_rockchip pcie@fe170000: PCIe-2 Link Fail which is a bit more acceptable (to me). The other option would be to disable the PCIe2 PHYs/controllers in the DT, which I'm not too fond of. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
113 lines
2.8 KiB
Plaintext
113 lines
2.8 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SPL_GPIO=y
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CONFIG_SF_DEFAULT_SPEED=24000000
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CONFIG_SF_DEFAULT_MODE=0x2000
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CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar"
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CONFIG_ROCKCHIP_RK3588=y
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CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
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CONFIG_SPL_SERIAL=y
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CONFIG_TARGET_JAGUAR_RK3588=y
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CONFIG_DEBUG_UART_BASE=0xfeb50000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SYS_LOAD_ADDR=0xc00800
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CONFIG_PCI=y
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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# CONFIG_BOOTMETH_VBE is not set
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CONFIG_LEGACY_IMAGE_FORMAT=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_CYCLIC=y
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_PAD_TO=0x7f8000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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CONFIG_SPL_ATF=y
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# CONFIG_BOOTM_NETBSD is not set
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# CONFIG_BOOTM_PLAN9 is not set
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# CONFIG_BOOTM_RTEMS is not set
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# CONFIG_BOOTM_VXWORKS is not set
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# CONFIG_CMD_ELF is not set
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CONFIG_CMD_ADC=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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# CONFIG_CMD_SF is not set
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_MII is not set
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# CONFIG_CMD_BLOCK_CACHE is not set
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# CONFIG_CMD_EFICONFIG is not set
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EROFS=y
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CONFIG_CMD_SQUASHFS=y
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# CONFIG_SPL_DOS_PARTITION is not set
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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# CONFIG_OF_TAG_MIGRATE is not set
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CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SPL_SYSCON=y
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CONFIG_BUTTON=y
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CONFIG_BUTTON_ADC=y
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CONFIG_SPL_CLK=y
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CONFIG_CLK_GPIO=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_SUPPORT_EMMC_RPMB=y
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CONFIG_MMC_IO_VOLTAGE=y
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CONFIG_SPL_MMC_IO_VOLTAGE=y
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CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_SPL_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS400_ES_SUPPORT=y
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CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_SPL_MMC_HS400_SUPPORT=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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# CONFIG_SPI_FLASH is not set
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CONFIG_SF_DEFAULT_BUS=5
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_DWC_ETH_QOS=y
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CONFIG_DWC_ETH_QOS_ROCKCHIP=y
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CONFIG_NVME_PCI=y
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CONFIG_PCIE_DW_ROCKCHIP=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_SPL_RAM=y
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CONFIG_SCSI=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_ROCKCHIP_SPI=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_GENERIC=y
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CONFIG_ERRNO_STR=y
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