forked from OERV-BSP/u-boot
7d8c3fa26c
SPL_TEXT_BASE is used as the load address for the main domain SPL on k3 platforms. Since the config value is the same for every board, this patch sets the value 0x80080000 as default for all 64-bit ARCH_K3, 0x43c00000 as default for the R5 cores and deletes the instances of SPL_TEXT_BASE in individual defconfigs. Signed-off-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
186 lines
4.7 KiB
Plaintext
186 lines
4.7 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_ARCH_K3=y
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CONFIG_SYS_MALLOC_LEN=0x2000000
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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CONFIG_SPL_GPIO=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_SOC_K3_AM642=y
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CONFIG_K3_ATF_LOAD_ADDR=0x701c0000
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CONFIG_TARGET_PHYCORE_AM64X_A53=y
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CONFIG_PHYTEC_SOM_DETECTION=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_OFFSET=0x680000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_DM_GPIO=y
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CONFIG_SPL_DM_SPI=y
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CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-phyboard-electra-rdk"
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CONFIG_OF_LIBFDT_OVERLAY=y
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CONFIG_DM_RESET=y
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CONFIG_SPL_MMC=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL_STACK_R_ADDR=0x82000000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x80a00000
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CONFIG_SPL_BSS_MAX_SIZE=0x80000
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CONFIG_SPL_STACK_R=y
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CONFIG_ENV_OFFSET_REDUND=0x6c0000
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CONFIG_SPL_FS_FAT=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_EFI_CAPSULE_ON_DISK=y
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CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
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CONFIG_BOOTSTD_FULL=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb"
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CONFIG_DEFAULT_FDT_FILE="oftree"
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CONFIG_BOARD_LATE_INIT=y
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CONFIG_SPL_MAX_SIZE=0x180000
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CONFIG_SPL_BOARD_INIT=y
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_SYS_MALLOC=y
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CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
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CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
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CONFIG_SPL_DMA=y
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CONFIG_SPL_ENV_SUPPORT=y
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CONFIG_SPL_ETH=y
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CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
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CONFIG_SPL_I2C=y
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CONFIG_SPL_DM_MAILBOX=y
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CONFIG_SPL_DM_SPI_FLASH=y
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CONFIG_SPL_NET=y
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CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot A53 SPL"
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CONFIG_SPL_POWER_DOMAIN=y
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CONFIG_SPL_RAM_DEVICE=y
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# CONFIG_SPL_SPI_FLASH_TINY is not set
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CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
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CONFIG_SPL_YMODEM_SUPPORT=y
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# CONFIG_CMD_BOOTEFI_HELLO is not set
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CONFIG_CMD_BOOTEFI_SELFTEST=y
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CONFIG_CMD_ASKENV=y
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CONFIG_CMD_NVEDIT_EFI=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_REMOTEPROC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EFIDEBUG=y
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CONFIG_CMD_RTC=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_SMC=y
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor"
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CONFIG_MULTI_DTB_FIT=y
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CONFIG_SPL_MULTI_DTB_FIT=y
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CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_NOWHERE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_SYS_MMC_ENV_DEV=1
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SPL_SYSCON=y
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CONFIG_SPL_OF_TRANSLATE=y
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_SPL_CLK_CCF=y
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CONFIG_CLK_CCF=y
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CONFIG_CLK_TI_SCI=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_MTD=y
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CONFIG_DFU_RAM=y
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CONFIG_DFU_SF=y
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CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
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CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
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CONFIG_DMA_CHANNELS=y
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CONFIG_TI_K3_NAVSS_UDMA=y
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CONFIG_TI_SCI_PROTOCOL=y
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CONFIG_DA8XX_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
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CONFIG_SYS_I2C_OMAP24XX=y
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CONFIG_DM_MAILBOX=y
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CONFIG_K3_SEC_PROXY=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_SPL_MMC_HS400_SUPPORT=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ADMA=y
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CONFIG_SPL_MMC_SDHCI_ADMA=y
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CONFIG_MMC_SDHCI_AM654=y
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CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SFDP_SUPPORT=y
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# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
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CONFIG_SPI_FLASH_SOFT_RESET=y
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CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_MT35XU=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_MULTIPLEXER=y
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CONFIG_MUX_MMIO=y
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CONFIG_PHY_TI_DP83867=y
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CONFIG_PHY_FIXED=y
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CONFIG_TI_AM65_CPSW_NUSS=y
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CONFIG_PHY=y
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CONFIG_SPL_PHY=y
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CONFIG_PHY_CADENCE_TORRENT=y
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CONFIG_PHY_J721E_WIZ=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_PINCTRL_SINGLE=y
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CONFIG_POWER_DOMAIN=y
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CONFIG_TI_SCI_POWER_DOMAIN=y
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CONFIG_K3_SYSTEM_CONTROLLER=y
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CONFIG_REMOTEPROC_TI_K3_ARM64=y
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CONFIG_RESET_TI_SCI=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_RV3028=y
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CONFIG_DM_SERIAL=y
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CONFIG_SOC_DEVICE=y
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CONFIG_SOC_DEVICE_TI_K3=y
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CONFIG_SOC_TI=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_CADENCE_QSPI=y
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CONFIG_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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CONFIG_SYSRESET_TI_SCI=y
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CONFIG_DM_THERMAL=y
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CONFIG_USB=y
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CONFIG_DM_USB_GADGET=y
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CONFIG_SPL_DM_USB_GADGET=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_CDNS3=y
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CONFIG_USB_CDNS3_GADGET=y
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CONFIG_USB_CDNS3_HOST=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
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CONFIG_USB_GADGET_VENDOR_NUM=0x0451
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CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
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CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_USB_FUNCTION_MASS_STORAGE=y
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CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
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