forked from OERV-BSP/u-boot
e246e2b658
If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at arch/arm/cpu/armv8/start.S. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2024 9elements GmbH
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* Physical memory map */
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/* SECURE_FLASH */
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#define SBSA_SECURE_FLASH_BASE_ADDR 0x00000000
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#define SBSA_SECURE_FLASH_LENGTH 0x10000000
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/* FLASH */
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#define SBSA_FLASH_BASE_ADDR 0x10000000
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#define SBSA_FLASH_LENGTH 0x10000000
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/* PERIPH */
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#define SBSA_PERIPH_BASE_ADDR 0x40000000
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/* GIC_DIST */
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#define SBSA_GIC_DIST_BASE_ADDR 0x40060000
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#define SBSA_GIC_DIST_LENGTH 0x00020000
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#define SBSA_GIC_VBASE_ADDR 0x2c020000
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#define SBSA_GIC_VBASE_LENGTH 0x00010000
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#define SBSA_GIC_HBASE_ADDR 0x2c010000
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#define SBSA_GIC_HBASE_LENGTH 0x00010000
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/* GIC_REDIST */
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#define SBSA_GIC_REDIST_BASE_ADDR 0x40080000
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#define SBSA_GIC_REDIST_LENGTH 0x04000000
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/* GIC_ITS */
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#define SBSA_GIC_ITS_BASE_ADDR 0x44081000
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/* UART */
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#define SBSA_UART_BASE_ADDR 0x60000000
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#define SBSA_UART_LENGTH 0x00001000
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/* SMMU */
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#define SBSA_SMMU_BASE_ADDR 0x60050000
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/* SATA */
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#define SBSA_AHCI_BASE_ADDR 0x60100000
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#define SBSA_AHCI_LENGTH 0x00010000
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/* xHCI */
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#define SBSA_XHCI_BASE_ADDR 0x60110000
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#define SBSA_XHCI_LENGTH 0x00010000
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/* PIO */
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#define SBSA_PIO_BASE_ADDR 0x7fff0000
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#define SBSA_PIO_LENGTH 0x00010000
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/* PCIE_MMIO */
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#define SBSA_PCIE_MMIO_BASE_ADDR 0x80000000
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#define SBSA_PCIE_MMIO_LENGTH 0x70000000
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#define SBSA_PCIE_MMIO_END 0xefffffff
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/* PCIE_ECAM */
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#define SBSA_PCIE_ECAM_BASE_ADDR 0xf0000000
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#define SBSA_PCIE_ECAM_LENGTH 0x10000000
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#define SBSA_PCIE_ECAM_END 0xffffffff
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/* PCIE_MMIO_HIGH */
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#ifdef __ACPI__
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#define SBSA_PCIE_MMIO_HIGH_BASE_ADDR 0x100000000
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#define SBSA_PCIE_MMIO_HIGH_LENGTH 0xFF00000000
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#define SBSA_PCIE_MMIO_HIGH_END 0xFFFFFFFFFF
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#else
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#define SBSA_PCIE_MMIO_HIGH_BASE_ADDR 0x100000000ULL
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#define SBSA_PCIE_MMIO_HIGH_LENGTH 0xFF00000000ULL
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#define SBSA_PCIE_MMIO_HIGH_END 0xFFFFFFFFFFULL
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#endif
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/* MEM */
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#ifdef __ACPI__
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#define SBSA_MEM_BASE_ADDR 0x10000000000
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#else
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#define SBSA_MEM_BASE_ADDR 0x10000000000ULL
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#endif
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#define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR
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#define CFG_SYS_INIT_RAM_SIZE 0x1000000
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE SBSA_GIC_DIST_BASE_ADDR
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#define GICR_BASE SBSA_GIC_REDIST_BASE_ADDR
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#endif /* __CONFIG_H */
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