forked from OERV-BSP/u-boot
7576ab2fac
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
31 lines
811 B
Plaintext
31 lines
811 B
Plaintext
CONFIG_RISCV=y
|
|
CONFIG_TEXT_BASE=0x21200000
|
|
CONFIG_SYS_MALLOC_LEN=0x800000
|
|
CONFIG_NR_DRAM_BANKS=1
|
|
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000
|
|
CONFIG_ENV_SIZE=0x20000
|
|
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
|
|
CONFIG_DEBUG_UART_BASE=0x40600000
|
|
CONFIG_DEBUG_UART_CLOCK=1000000
|
|
CONFIG_SYS_CLK_FREQ=100000000
|
|
CONFIG_BOOT_SCRIPT_OFFSET=0x0
|
|
CONFIG_SYS_LOAD_ADDR=0x80200000
|
|
CONFIG_DEBUG_UART=y
|
|
CONFIG_TARGET_XILINX_MBV=y
|
|
CONFIG_FIT=y
|
|
CONFIG_DISTRO_DEFAULTS=y
|
|
CONFIG_DISPLAY_CPUINFO=y
|
|
CONFIG_DISPLAY_BOARDINFO=y
|
|
# CONFIG_BOARD_LATE_INIT is not set
|
|
# CONFIG_CMD_MII is not set
|
|
CONFIG_CMD_TIMER=y
|
|
CONFIG_OF_EMBED=y
|
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
CONFIG_DM_MTD=y
|
|
CONFIG_DEBUG_UART_ANNOUNCE=y
|
|
CONFIG_DEBUG_UART_SKIP_INIT=y
|
|
CONFIG_XILINX_UARTLITE=y
|
|
CONFIG_XILINX_TIMER=y
|
|
CONFIG_PANIC_HANG=y
|