forked from OERV-BSP/u-boot
9f0253c61a
Add missing cache cleanup before cache disable: * Flush and invalidate L1 D$ before disabling. Flush and invalidate SLC before L1 D$ disabling (as it will be bypassed for data) Otherwise we can lose some data when we disable L1 D$ if this data isn't flushed to next level cache. Or we can get wrong data if L1 D$ has some entries after enable which we modified when the L1 D$ was disabled. * Invalidate L1 I$ before disabling. Otherwise we can execute wrong instructions after L1 I$ enable if we modified any code when L1 I$ was disabled. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>