forked from OERV-BSP/u-boot
9065b87f35
The family of PCA9450 PMICs have the ability to perform system resets.
Restarting via PMIC is preferred method of restarting the system as all
the peripherals are brought to a know state after a power-cycle. The
PCA9450 features a cold restart procedure which is initiated by an I2C
command 0x14 to the SW_RST register.
Support in Linux for restarting via PCA9450 PMIC has been added by
Linux commit 6157e62b07d9 ("regulator: pca9450: Add restart handler").
Now add support for it also in the U-Boot via sysreset framework.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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*/
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#ifndef PCA9450_H_
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#define PCA9450_H_
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#define PCA9450_REGULATOR_DRIVER "pca9450_regulator"
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enum {
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PCA9450_REG_DEV_ID = 0x00,
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PCA9450_INT1 = 0x01,
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PCA9450_INT1_MSK = 0x02,
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PCA9450_STATUS1 = 0x03,
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PCA9450_STATUS2 = 0x04,
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PCA9450_PWRON_STAT = 0x05,
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PCA9450_SW_RST = 0x06,
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PCA9450_PWR_CTRL = 0x07,
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PCA9450_RESET_CTRL = 0x08,
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PCA9450_CONFIG1 = 0x09,
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PCA9450_CONFIG2 = 0x0A,
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PCA9450_BUCK123_DVS = 0x0C,
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PCA9450_BUCK1OUT_LIMIT = 0x0D,
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PCA9450_BUCK2OUT_LIMIT = 0x0E,
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PCA9450_BUCK3OUT_LIMIT = 0x0F,
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PCA9450_BUCK1CTRL = 0x10,
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PCA9450_BUCK1OUT_DVS0 = 0x11,
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PCA9450_BUCK1OUT_DVS1 = 0x12,
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PCA9450_BUCK2CTRL = 0x13,
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PCA9450_BUCK2OUT_DVS0 = 0x14,
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PCA9450_BUCK2OUT_DVS1 = 0x15,
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PCA9450_BUCK3CTRL = 0x16,
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PCA9450_BUCK3OUT_DVS0 = 0x17,
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PCA9450_BUCK3OUT_DVS1 = 0x18,
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PCA9450_BUCK4CTRL = 0x19,
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PCA9450_BUCK4OUT = 0x1A,
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PCA9450_BUCK5CTRL = 0x1B,
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PCA9450_BUCK5OUT = 0x1C,
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PCA9450_BUCK6CTRL = 0x1D,
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PCA9450_BUCK6OUT = 0x1E,
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PCA9450_LDO_AD_CTRL = 0x20,
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PCA9450_LDO1CTRL = 0x21,
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PCA9450_LDO2CTRL = 0x22,
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PCA9450_LDO3CTRL = 0x23,
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PCA9450_LDO4CTRL = 0x24,
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PCA9450_LDO5CTRL_L = 0x25,
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PCA9450_LDO5CTRL_H = 0x26,
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PCA9450_LOADSW_CTRL = 0x2A,
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PCA9450_VRFLT1_STS = 0x2B,
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PCA9450_VRFLT2_STS = 0x2C,
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PCA9450_VRFLT1_MASK = 0x2D,
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PCA9450_VRFLT2_MASK = 0x2E,
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PCA9450_REG_NUM,
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};
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#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
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int power_pca9450_init(unsigned char bus, unsigned char addr);
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enum {
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NXP_CHIP_TYPE_PCA9450A = 0,
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NXP_CHIP_TYPE_PCA9450BC,
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NXP_CHIP_TYPE_PCA9451A,
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NXP_CHIP_TYPE_PCA9452,
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NXP_CHIP_TYPE_AMOUNT
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};
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#define PCA9450_DVS_BUCK_RUN_MASK 0x7f
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#define PCA9450_LDO12_MASK 0x07
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#define PCA9450_LDO34_MASK 0x1f
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#define PCA9450_LDO5_MASK 0x0f
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#define PCA9450_PMIC_RESET_WDOG_B_CFG_MASK 0xc0
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#define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40
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#define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80
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#define PCA9450_SW_RST_COLD_RST 0x14
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#endif
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