forked from OERV-BSP/u-boot
998da69da6
Update defconfig to make use of U-Boot SPL to initialize DH STM32MP13xx DHCOM DHSBC SoM and board. This is largely a move of SPL enablement from DH STM32MP15xx DHSOM defconfigs into generic DH STM32MP1xx defconfig . Support for SPI NOR chips which are not used on STM32MP13xx DHCOR are moved into STM32MP15xx DHSOM defconfigs. Changes to STM32MP13xx DHCOR defconfig then enable SPL support, CCF in SPL to configure clock, pin configuration support in SPL, and OpTee OS start support in U-Boot. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
63 lines
1.6 KiB
Plaintext
63 lines
1.6 KiB
Plaintext
#include <configs/stm32mp_dhsom.config>
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CONFIG_ARM=y
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CONFIG_ARCH_STM32MP=y
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CONFIG_SYS_MALLOC_F_LEN=0x1c0000
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000
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CONFIG_ENV_OFFSET=0x3E0000
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CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp135f-dhcor-dhsbc"
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CONFIG_STM32MP13X=y
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CONFIG_DDR_CACHEABLE_SIZE=0x8000000
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CONFIG_TARGET_ST_STM32MP13X=y
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CONFIG_ENV_OFFSET_REDUND=0x3F0000
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CONFIG_STM32MP15_PWR=y
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CONFIG_ARMV7_NONSEC=y
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CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
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CONFIG_ARMV7_PSCI_NR_CPUS=2
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# CONFIG_ARMV7_LPAE is not set
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CONFIG_SYS_MEMTEST_START=0xc0000000
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CONFIG_SYS_MEMTEST_END=0xc4000000
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CONFIG_SYS_MEM_TOP_HIDE=0x2000000
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CONFIG_BOOTSTAGE_RECORD_COUNT=100
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CONFIG_BOOTDELAY=3
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CONFIG_BOOTM_OPTEE=y
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_CMD_ASKENV=y
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CONFIG_CMD_ERASEENV=y
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CONFIG_CMD_LSBLK=y
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CONFIG_CMD_CAT=y
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CONFIG_CMD_SETEXPR_FMT=y
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CONFIG_CMD_XXD=y
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CONFIG_CMD_RNG=y
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CONFIG_CMD_LOG=y
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CONFIG_CMD_UBI=y
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CONFIG_ENV_IS_NOWHERE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ENV_MMC_USE_DT=y
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CONFIG_ENV_SPI_MAX_HZ=50000000
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CONFIG_SET_DFU_ALT_INFO=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x50
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CONFIG_ENV_MMC_DEVICE_INDEX=0
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CONFIG_ENV_MMC_EMMC_HW_PARTITION=1
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_RNG=y
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CONFIG_RNG_STM32=y
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CONFIG_USB_ONBOARD_HUB=y
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CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
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CONFIG_ERRNO_STR=y
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CONFIG_OPTEE_LIB=y
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CONFIG_OPTEE_IMAGE=y
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CONFIG_OPTEE_TZDRAM_SIZE=0x02000000
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CONFIG_SPL_TEXT_BASE=0x2FFE0000
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CONFIG_SPL_CLK_CCF=y
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CONFIG_SPL_CLK_COMPOSITE_CCF=y
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# CONFIG_SPL_SHA1 is not set
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# CONFIG_SPL_SHA256 is not set
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CONFIG_SPL_HAVE_INIT_STACK=y
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CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
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CONFIG_SPL_PINCTRL=y
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CONFIG_SPL_PINCTRL_GENERIC=y
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CONFIG_SPL_PINMUX=y
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CONFIG_SPL_PINCONF=y
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
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