forked from OERV-BSP/u-boot
f8efc68b30
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> says: This series adds support for Xilinx qspi parallel and stacked memeories. In parallel mode, the current implementation assumes that a maximum of two flashes are connected. The QSPI controller splits the data evenly between both the flashes so, both the flashes that are connected in parallel mode should be identical. During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in nor->flags. In stacked mode the current implementation assumes that a maximum of two flashes are connected and both the flashes are of same make but can differ in sizes. So, except the sizes all other flash parameters of both the flashes are identical. Spi-nor will pass on the appropriate flash select flag to low level driver, and it will select pass all the data to that particular flash. Write operation in parallel mode are performed in page size * 2 chunks as each write operation results in writing both the flashes. For doubling the address space each operation is performed at addr/2 flash offset, where addr is the address specified by the user. Similarly for read and erase operations it will read from both flashes, so size and offset are divided by 2 and send to flash.
162 lines
4.1 KiB
Plaintext
162 lines
4.1 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SPL_SYS_DCACHE_OFF=y
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CONFIG_SYS_L2CACHE_OFF=y
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CONFIG_ARCH_ZYNQ=y
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CONFIG_TEXT_BASE=0x4000000
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CONFIG_SF_DEFAULT_SPEED=30000000
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CONFIG_ENV_OFFSET=0xE00000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
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CONFIG_OF_LIBFDT_OVERLAY=y
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CONFIG_SPL_STACK_R_ADDR=0x200000
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CONFIG_SPL_STACK=0xfffffe00
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x100000
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CONFIG_SPL_BSS_MAX_SIZE=0x100000
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CONFIG_SPL_STACK_R=y
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CONFIG_SYS_BOOTM_LEN=0x3c00000
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CONFIG_SYS_LOAD_ADDR=0x0
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CONFIG_SPL=y
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CONFIG_ENV_OFFSET_REDUND=0xE40000
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CONFIG_CMD_FRU=y
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CONFIG_CMD_ZYNQ_AES=y
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CONFIG_SYS_MEMTEST_START=0x00000000
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CONFIG_SYS_MEMTEST_END=0x00001000
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CONFIG_REMAKE_ELF=y
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CONFIG_SYS_CUSTOM_LDSCRIPT=y
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CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
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CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
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CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
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CONFIG_FIT=y
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CONFIG_FIT_SIGNATURE=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_PRINT=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
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CONFIG_LEGACY_IMAGE_FORMAT=y
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CONFIG_DISTRO_DEFAULTS=y
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_USE_PREBOOT=y
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CONFIG_SYS_PBSIZE=2071
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CONFIG_CLOCKS=y
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CONFIG_SPL_MAX_SIZE=0x30000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_SYS_MALLOC=y
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CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
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CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
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CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb"
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CONFIG_SPL_FPGA=y
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CONFIG_SPL_OS_BOOT=y
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CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
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CONFIG_SYS_MAXARGS=32
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# CONFIG_BOOTM_NETBSD is not set
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_THOR_DOWNLOAD=y
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CONFIG_THOR_RESET_OFF=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_SYS_ALT_MEMTEST=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_FPGA_LOADBP=y
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CONFIG_CMD_FPGA_LOADFS=y
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CONFIG_CMD_FPGA_LOADMK=y
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CONFIG_CMD_FPGA_LOADP=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_MMC_SPEED_MODE_SET=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_NAND_LOCK_UNLOCK=y
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CONFIG_CMD_SF_TEST=y
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CONFIG_CMD_USB=y
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CONFIG_BOOTP_MAY_FAIL=y
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_NFS=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EFIDEBUG=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_TIMER=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_SQUASHFS=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_CMD_MTDPARTS_SPREAD=y
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CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
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CONFIG_CMD_UBI=y
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CONFIG_OF_BOARD=y
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CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0"
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CONFIG_ENV_IS_NOWHERE=y
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CONFIG_ENV_IS_IN_FAT=y
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CONFIG_ENV_IS_IN_NAND=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_NETCONSOLE=y
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CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SIMPLE_PM_BUS=y
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CONFIG_DFU_TIMEOUT=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_DFU_SF=y
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CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_CADENCE=y
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CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_MISC=y
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CONFIG_NVMEM=y
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CONFIG_I2C_EEPROM=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_SHOW_PROGRESS=10
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CONFIG_CFI_FLASH=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_SYS_FLASH_QUIET_TEST=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_ZYNQ=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_XILINX=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_MII=y
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CONFIG_ZYNQ_GEM=y
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CONFIG_POWER_DOMAIN=y
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CONFIG_ARM_DCC=y
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CONFIG_ZYNQ_SERIAL=y
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CONFIG_SPI_ADVANCE=y
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CONFIG_ZYNQ_SPI=y
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CONFIG_ZYNQ_QSPI=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_ULPI_VIEWPORT=y
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CONFIG_USB_ULPI=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
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CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
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CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
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CONFIG_CI_UDC=y
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CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_SYS_TIMER_COUNTS_DOWN=y
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CONFIG_SPL_GZIP=y
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