forked from OERV-BSP/u-boot
3dbff9eecc
Designed before a standard set of cache management operations defined in RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the customized extension XTheadCMO, which has been used in the CV1800B port of U-Boot. This patch splits XTheadCMO-related code into a generic module, allowing SoCs shipping T-Head cores to share the code. Link: https://github.com/XUANTIE-RV/thead-extension-spec Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
14 lines
273 B
Plaintext
14 lines
273 B
Plaintext
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
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config SOPHGO_CV1800B
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bool
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select ARCH_EARLY_INIT_R
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select SYS_CACHE_SHIFT_6
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select SYS_CACHE_THEAD_CMO
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER
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imply CMD_CPU
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