forked from OERV-BSP/u-boot
7a7c10054d
Agilex7 M-series reuse the clock driver from Agilex. Signed-off-by: Tingting Meng <tingting.meng@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
12 lines
405 B
Makefile
12 lines
405 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2018-2021 Marek Vasut <marex@denx.de>
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#
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obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
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obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
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obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
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obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
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obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o
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