forked from OERV-BSP/u-boot
3bab8f17fb
Enable cache for AM62p to optimize performance of CPU to access data from memory. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
71 lines
1.4 KiB
C
71 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board specific initialization for AM62Px platforms
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*
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#include <efi_loader.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <cpu_func.h>
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#include <dm/uclass.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <spl.h>
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#include <asm/arch/k3-ddr.h>
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#include "../common/fdt_ops.h"
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struct efi_fw_image fw_images[] = {
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{
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.image_type_id = AM62PX_SK_TIBOOT3_IMAGE_GUID,
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.fw_name = u"AM62PX_SK_TIBOOT3",
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.image_index = 1,
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},
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{
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.image_type_id = AM62PX_SK_SPL_IMAGE_GUID,
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.fw_name = u"AM62PX_SK_SPL",
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.image_index = 2,
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},
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{
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.image_type_id = AM62PX_SK_UBOOT_IMAGE_GUID,
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.fw_name = u"AM62PX_SK_UBOOT",
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.image_index = 3,
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}
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};
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struct efi_capsule_update_info update_info = {
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.dfu_string = "sf 0:0=tiboot3.bin raw 0 80000;"
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"tispl.bin raw 80000 200000;u-boot.img raw 280000 400000",
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.num_images = ARRAY_SIZE(fw_images),
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.images = fw_images,
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};
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#if IS_ENABLED(CONFIG_SPL_BUILD)
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void spl_board_init(void)
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{
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enable_caches();
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}
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#endif
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#if defined(CONFIG_XPL_BUILD)
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void spl_perform_fixups(struct spl_image_info *spl_image)
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{
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if (IS_ENABLED(CONFIG_K3_DDRSS)) {
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if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
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fixup_ddr_driver_for_ecc(spl_image);
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} else {
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fixup_memory_node(spl_image);
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}
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}
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#endif
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#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
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int board_late_init(void)
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{
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ti_set_fdt_env(NULL, NULL);
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return 0;
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}
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#endif
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