forked from OERV-BSP/u-boot
e875813600
TH1520 SoC ships two MAC controllers based on Designware Ethernet IP that are capable of Gigabit operation. Describe them in SoC devicetree and enable them for Lichee Pi 4A. Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
531 lines
13 KiB
Plaintext
531 lines
13 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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#include <dt-bindings/clock/thead,th1520-clk-ap.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "thead,th1520";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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bootph-pre-ram;
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timebase-frequency = <3000000>;
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c910_0: cpu@0 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <0>;
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bootph-pre-ram;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_1: cpu@1 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <1>;
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bootph-pre-ram;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_2: cpu@2 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <2>;
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bootph-pre-ram;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_3: cpu@3 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <3>;
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bootph-pre-ram;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <1048576>;
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cache-sets = <1024>;
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cache-unified;
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};
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};
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_24m";
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#clock-cells = <0>;
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};
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osc_32k: 32k-oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_32k";
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#clock-cells = <0>;
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};
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aonsys_clk: clock-73728000 {
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compatible = "fixed-clock";
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clock-frequency = <73728000>;
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clock-output-names = "aonsys_clk";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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plic: interrupt-controller@ffd8000000 {
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compatible = "thead,th1520-plic", "thead,c900-plic";
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reg = <0xff 0xd8000000 0x0 0x01000000>;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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riscv,ndev = <240>;
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};
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clint: timer@ffdc000000 {
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compatible = "thead,th1520-clint", "thead,c900-clint";
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reg = <0xff 0xdc000000 0x0 0x00010000>;
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bootph-pre-ram;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
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<&cpu1_intc 3>, <&cpu1_intc 7>,
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<&cpu2_intc 3>, <&cpu2_intc 7>,
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<&cpu3_intc 3>, <&cpu3_intc 7>;
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};
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uart0: serial@ffe7014000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xe7014000 0x0 0x100>;
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bootph-pre-ram;
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interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
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clock-names = "buadclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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gmac1: ethernet@ffe7060000 {
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compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
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reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
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reg-names = "dwmac", "apb";
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interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>;
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clock-names = "stmmaceth", "pclk";
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snps,pbl = <32>;
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snps,fixed-burst;
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snps,multicast-filter-bins = <64>;
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snps,perfect-filter-entries = <32>;
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status = "disabled";
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mdio1: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gmac0: ethernet@ffe7070000 {
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compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
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reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>;
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reg-names = "dwmac", "apb";
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interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>;
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clock-names = "stmmaceth", "pclk";
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snps,pbl = <32>;
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snps,fixed-burst;
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snps,multicast-filter-bins = <64>;
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snps,perfect-filter-entries = <32>;
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status = "disabled";
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mdio0: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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emmc: mmc@ffe7080000 {
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compatible = "thead,th1520-dwcmshc";
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reg = <0xff 0xe7080000 0x0 0x10000>;
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interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_EMMC_SDIO>;
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clock-names = "core";
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status = "disabled";
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};
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sdio0: mmc@ffe7090000 {
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compatible = "thead,th1520-dwcmshc";
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reg = <0xff 0xe7090000 0x0 0x10000>;
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interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_EMMC_SDIO>;
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clock-names = "core";
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status = "disabled";
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};
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sdio1: mmc@ffe70a0000 {
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compatible = "thead,th1520-dwcmshc";
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reg = <0xff 0xe70a0000 0x0 0x10000>;
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interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_EMMC_SDIO>;
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clock-names = "core";
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status = "disabled";
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};
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uart1: serial@ffe7f00000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xe7f00000 0x0 0x100>;
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interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
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clock-names = "buadclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@ffe7f04000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xe7f04000 0x0 0x100>;
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interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
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clock-names = "buadclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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gpio2: gpio@ffe7f34000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xe7f34000 0x0 0x1000>;
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clocks = <&clk CLK_GPIO2>;
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clock-names = "bus";
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio3: gpio@ffe7f38000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xe7f38000 0x0 0x1000>;
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clocks = <&clk CLK_GPIO3>;
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clock-names = "bus";
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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padctrl1_apsys: pinctrl@ffe7f3c000 {
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compatible = "thead,th1520-pinctrl";
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reg = <0xff 0xe7f3c000 0x0 0x1000>;
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clocks = <&clk CLK_PADCTRL1>;
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thead,pad-group = <2>;
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};
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gpio0: gpio@ffec005000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xec005000 0x0 0x1000>;
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clocks = <&clk CLK_GPIO0>;
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clock-names = "bus";
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@ffec006000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xff 0xec006000 0x0 0x1000>;
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clocks = <&clk CLK_GPIO1>;
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clock-names = "bus";
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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padctrl0_apsys: pinctrl@ffec007000 {
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compatible = "thead,th1520-pinctrl";
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reg = <0xff 0xec007000 0x0 0x1000>;
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clocks = <&clk CLK_PADCTRL0>;
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thead,pad-group = <3>;
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};
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uart2: serial@ffec010000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xec010000 0x0 0x4000>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
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clock-names = "buadclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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clk: clock-controller@ffef010000 {
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compatible = "thead,th1520-clk-ap";
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reg = <0xff 0xef010000 0x0 0x1000>;
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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timer0: timer@ffefc32000 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xefc32000 0x0 0x14>;
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clocks = <&clk CLK_PERI_APB_PCLK>;
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clock-names = "timer";
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interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer1: timer@ffefc32014 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xefc32014 0x0 0x14>;
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clocks = <&clk CLK_PERI_APB_PCLK>;
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clock-names = "timer";
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer2: timer@ffefc32028 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xefc32028 0x0 0x14>;
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clocks = <&clk CLK_PERI_APB_PCLK>;
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clock-names = "timer";
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer3: timer@ffefc3203c {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xefc3203c 0x0 0x14>;
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clocks = <&clk CLK_PERI_APB_PCLK>;
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clock-names = "timer";
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interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart4: serial@fff7f08000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xf7f08000 0x0 0x4000>;
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
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clock-names = "buadclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart5: serial@fff7f0c000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff 0xf7f0c000 0x0 0x4000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
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clock-names = "buadclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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ddrc: ddrc@fffd000000 {
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compatible = "thead,th1520-ddrc";
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reg = <0xff 0xfd000000 0x0 0x1000000>,
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<0xff 0xfe000000 0x0 0x1000000>,
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<0xff 0xff000000 0x0 0x4000>,
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<0xff 0xff005000 0x0 0x1000>;
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reg-names = "phy-0", "phy-1", "ctrl", "sys";
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bootph-pre-ram;
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};
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timer4: timer@ffffc33000 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xffc33000 0x0 0x14>;
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clocks = <&clk CLK_PERI_APB_PCLK>;
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clock-names = "timer";
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer5: timer@ffffc33014 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xffc33014 0x0 0x14>;
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clocks = <&clk CLK_PERI_APB_PCLK>;
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clock-names = "timer";
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interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer6: timer@ffffc33028 {
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compatible = "snps,dw-apb-timer";
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reg = <0xff 0xffc33028 0x0 0x14>;
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clocks = <&clk CLK_PERI_APB_PCLK>;
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clock-names = "timer";
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer7: timer@ffffc3303c {
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compatible = "snps,dw-apb-timer";
|
|
reg = <0xff 0xffc3303c 0x0 0x14>;
|
|
clocks = <&clk CLK_PERI_APB_PCLK>;
|
|
clock-names = "timer";
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ao_gpio0: gpio@fffff41000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xff 0xfff41000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
porte: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <32>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
padctrl_aosys: pinctrl@fffff4a000 {
|
|
compatible = "thead,th1520-pinctrl";
|
|
reg = <0xff 0xfff4a000 0x0 0x2000>;
|
|
clocks = <&aonsys_clk>;
|
|
thead,pad-group = <1>;
|
|
};
|
|
|
|
ao_gpio1: gpio@fffff52000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xff 0xfff52000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
portf: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <32>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|
|
};
|