forked from OERV-BSP/u-boot
bbf5f79bba
JH7110 drivers are missing support for CPU frequency scaling, so override upstream device-tree to use default clock rates for syscrg. This override duplicates a portion of jh7110-common-u-boot.dtsi file planned for removal. Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Leo Liang <ycliang@andestech.com>
105 lines
1.4 KiB
Plaintext
105 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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/ {
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timer {
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compatible = "riscv,timer";
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interrupts-extended = <&cpu0_intc 5>,
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<&cpu1_intc 5>,
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<&cpu2_intc 5>,
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<&cpu3_intc 5>,
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<&cpu4_intc 5>;
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};
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soc {
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bootph-pre-ram;
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dmc: dmc@15700000 {
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bootph-pre-ram;
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compatible = "starfive,jh7110-dmc";
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reg = <0x0 0x15700000 0x0 0x10000>,
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<0x0 0x13000000 0x0 0x10000>;
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resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
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<&syscrg JH7110_SYSRST_DDR_OSC>,
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<&syscrg JH7110_SYSRST_DDR_APB>;
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reset-names = "axi", "osc", "apb";
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clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
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clock-names = "pll1_out";
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clock-frequency = <2133>;
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};
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};
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};
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&clint {
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bootph-pre-ram;
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};
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&cpu0_intc {
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bootph-pre-ram;
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};
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&cpu1_intc {
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bootph-pre-ram;
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};
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&cpu2_intc {
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bootph-pre-ram;
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};
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&cpu3_intc {
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bootph-pre-ram;
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};
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&cpu4_intc {
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bootph-pre-ram;
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};
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&cpus {
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bootph-pre-ram;
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};
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&osc {
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bootph-pre-ram;
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};
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&gmac0_rgmii_rxin {
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bootph-pre-ram;
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};
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&gmac0_rmii_refin {
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bootph-pre-ram;
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};
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&gmac1_rgmii_rxin {
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bootph-pre-ram;
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};
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&gmac1_rmii_refin {
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bootph-pre-ram;
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};
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&aoncrg {
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bootph-pre-ram;
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};
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&pllclk {
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bootph-pre-ram;
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};
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&syscrg {
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assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
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bootph-pre-ram;
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};
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&stgcrg {
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bootph-pre-ram;
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};
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&sys_syscon {
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bootph-pre-ram;
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};
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