forked from OERV-BSP/u-boot
12b90ea3c2
TH1520 SoC ships DMA peripherals that could only reach the first 32-bit range of memory, for example, the GMAC controllers. Let's limit the usable top of RAM below 4GiB to ensure DMA allocations are accessible to all peripherals. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
38 lines
734 B
C
38 lines
734 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
|
|
*/
|
|
|
|
#include <fdtdec.h>
|
|
#include <init.h>
|
|
#include <asm/global_data.h>
|
|
#include <linux/sizes.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int dram_init(void)
|
|
{
|
|
return fdtdec_setup_mem_size_base();
|
|
}
|
|
|
|
int dram_init_banksize(void)
|
|
{
|
|
return fdtdec_setup_memory_banksize();
|
|
}
|
|
|
|
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
|
|
{
|
|
/*
|
|
* Ensure that we run from first 4GB so that all
|
|
* addresses used by U-Boot are 32bit addresses.
|
|
*
|
|
* This in-turn ensures that 32bit DMA capable
|
|
* devices work fine because DMA mapping APIs will
|
|
* provide 32bit DMA addresses only.
|
|
*/
|
|
if (gd->ram_top > SZ_4G)
|
|
return SZ_4G;
|
|
|
|
return gd->ram_top;
|
|
}
|