forked from OERV-BSP/u-boot
1d26da5a6a
Thanks for Jernej's JTAG debugging effort, it turns out that the BROM expects SP_IRQ to be saved and restored, when we want to enter back into FEL after the SPL's AArch64 stint. Save and restore SP_IRQ as part of the FEL state handling. The banked MRS/MSR access to SP_IRQ, without actually being in IRQ mode, was introduced with the ARMv7 virtualisation extensions. The Arm Cortex-A8 cores used in the A10/A13s or older F1C100s SoCs would not support that, but this code here is purely in the ARMv8/AArch64 code path, so it's safe to use unconditionally. Reported-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
72 lines
2.5 KiB
C
72 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration settings for the Allwinner A64 (sun50i) CPU
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*/
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#include <asm/arch/cpu.h>
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#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_XPL_BUILD)
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/* reserve space for BOOT0 header information */
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b reset
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.space 1532
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#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
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/*
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* Switch into AArch64 if needed.
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* Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
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*/
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tst x0, x0 // this is "b #0x84" in ARM
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b reset
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.space 0x78
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.word fel_stash - .
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.word 0xe24f000c // sub r0, pc, #12 // @(fel_stash - .)
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.word 0xe51f1010 // ldr r1, [pc, #-16] // fel_stash - .
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.word 0xe0800001 // add r0, r0, r1
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.word 0xe580d000 // str sp, [r0]
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.word 0xe580e004 // str lr, [r0, #4]
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.word 0xe10fe000 // mrs lr, CPSR
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.word 0xe580e008 // str lr, [r0, #8]
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.word 0xe101e300 // mrs lr, SP_irq
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.word 0xe580e014 // str lr, [r0, #20]
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.word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0}
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.word 0xe580e00c // str lr, [r0, #12]
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.word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0}
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.word 0xe580e010 // str lr, [r0, #16]
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#ifdef CONFIG_MACH_SUN55I_A523
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.word 0xee1cefbc // mrc 15, 0, lr, cr12, cr12, {5}
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.word 0xe31e0001 // tst lr, #1
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.word 0x0a000003 // beq cc <start32+0x48>
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.word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0}
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.word 0xe580e018 // str lr, [r0, #24]
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.word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7}
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.word 0xe580e01c // str lr, [r0, #28]
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#endif
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.word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS
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.word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE
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.word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG
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.word 0xe21000ff // ands r0, r0, #255 ; 0xff
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.word 0x159f102c // ldrne r1, [pc, #44] ; RVBAR_ALTERNATIVE
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.word 0xe59f002c // ldr r0, [pc, #44] ; CONFIG_*TEXT_BASE
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.word 0xe5810000 // str r0, [r1]
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.word 0xf57ff04f // dsb sy
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.word 0xf57ff06f // isb sy
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.word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR
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.word 0xe3800003 // orr r0, r0, #3
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.word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR
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.word 0xf57ff06f // isb sy
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.word 0xe320f003 // wfi
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.word 0xeafffffd // b @wfi
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.word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr
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.word SUNXI_SRAMC_BASE
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.word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant
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#ifdef CONFIG_XPL_BUILD
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.word CONFIG_SPL_TEXT_BASE
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#else
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.word CONFIG_TEXT_BASE
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#endif
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#else
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/* normal execution */
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b reset
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#endif
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