forked from OERV-BSP/u-boot
f9b4d051a7
This was only used on RK3288 Chromebooks and the EVB. If it follows the same pattern as for RK3399 Chromebooks where their maintainer (Simon) agreed[1] to removal of u-boot.rom on the basis that the generic u-boot-rockchip-spi.bin is now enough, let's do the same for RK3288 and remove the last Rockchip users of u-boot.rom (and HAS_ROM symbol). At the same time, remove HAS_ROM symbol from the RK3288 Chromebooks and EVB configs since they were used only for that. SYS_SPI_U_BOOT_OFFS offset in rockchip-u-boot.dtsi for the u-boot-img node of simple-bin-spi binman image matches the one used in u-boot.rom except for the EVB. The EVB doesn't have ROCKCHIP_SPI_IMAGE symbol enabled, so HAS_ROM had no effect anyway. Even if it had, this would not have been enough considering that SPL_SPI_LOAD symbol is not set, so U-Boot proper could not be loaded from SPI even if SPL/TPL does. Make sure u-boot-rockchip-spi.bin has the same size of u-boot.rom for Chromebooks as that seems to be important. [1] https://lore.kernel.org/u-boot/CAFLszTh-SewFod8dEOF3+e-wCE1qFF0CyxxR8CbQwy3BRW3k6w@mail.gmail.com/ Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-kevin Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
108 lines
1.6 KiB
Plaintext
108 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Rockchip Electronics Co., Ltd
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*/
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#include "rockchip-u-boot.dtsi"
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/ {
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aliases {
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mmc0 = &emmc;
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mmc1 = &sdmmc;
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mmc2 = &sdio0;
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mmc3 = &sdio1;
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};
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chosen {
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u-boot,spl-boot-order = \
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"same-as-spl", &emmc, &sdmmc;
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};
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dmc: dmc@ff610000 {
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compatible = "rockchip,rk3288-dmc", "syscon";
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reg = <0x0 0xff610000 0x0 0x3fc
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0x0 0xff620000 0x0 0x294
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0x0 0xff630000 0x0 0x3fc
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0x0 0xff640000 0x0 0x294>;
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clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
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<&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
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<&cru ARMCLK>;
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clock-names = "pclk_ddrupctl0", "pclk_publ0",
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"pclk_ddrupctl1", "pclk_publ1",
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"arm_clk";
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rockchip,cru = <&cru>;
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rockchip,grf = <&grf>;
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rockchip,noc = <&noc>;
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rockchip,pmu = <&pmu>;
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rockchip,sgrf = <&sgrf>;
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rockchip,sram = <&ddr_sram>;
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bootph-all;
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};
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noc: syscon@ffac0000 {
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compatible = "rockchip,rk3288-noc", "syscon";
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reg = <0x0 0xffac0000 0x0 0x2000>;
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bootph-all;
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};
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};
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&bus_intmem {
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ddr_sram: ddr-sram@1000 {
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compatible = "rockchip,rk3288-ddr-sram";
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reg = <0x1000 0x4000>;
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};
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};
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&cru {
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bootph-all;
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};
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&edp {
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clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
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clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
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};
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&gpio7 {
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bootph-all;
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};
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&grf {
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bootph-all;
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};
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&pmu {
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bootph-all;
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};
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&sgrf {
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bootph-all;
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};
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&uart0 {
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clock-frequency = <24000000>;
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};
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&uart1 {
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clock-frequency = <24000000>;
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};
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&uart2 {
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clock-frequency = <24000000>;
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};
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&uart3 {
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clock-frequency = <24000000>;
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};
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&vopb {
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bootph-some-ram;
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};
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&vopl {
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bootph-some-ram;
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};
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&xin24m {
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bootph-all;
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};
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