forked from OERV-BSP/u-boot
eda18cc2c3
enable text based default U-Boot Environment by enabling CONFIG_ENV_SOURCE_FILE and adding default environment file: board/siemens/capricorn/capricorn_cxg3.env Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Walter Schweizer <walter.schweizer@siemens.com>
58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017-2018 NXP
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* Copyright 2019 Siemens AG
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*/
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#ifndef __IMX8X_CAPRICORN_H
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#define __IMX8X_CAPRICORN_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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/* SPL config */
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#ifdef CONFIG_XPL_BUILD
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#define CFG_MALLOC_F_ADDR 0x00120000
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#endif /* CONFIG_XPL_BUILD */
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/* ENET1 connects to base board and MUX with ESAI */
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#define CFG_FEC_ENET_DEV 1
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#define CFG_FEC_MXC_PHYADDR 0x0
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/* EEPROM */
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#define EEPROM_I2C_BUS 0 /* I2C0 */
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#define EEPROM_I2C_ADDR 0x50
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/* PCA9552 */
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#define PCA9552_1_I2C_BUS 1 /* I2C1 */
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#define PCA9552_1_I2C_ADDR 0x60
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/* AHAB */
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#ifdef CONFIG_AHAB_BOOT
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#define AHAB_ENV "sec_boot=yes\0"
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#else
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#define AHAB_ENV "sec_boot=no\0"
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#endif
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/* Initial environment variables */
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#define CFG_EXTRA_ENV_SETTINGS \
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AHAB_ENV
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/* Default location for tftp and bootm */
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/* On CCP board, USDHC1 is for eMMC */
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#define CFG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_2 0x880000000
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/* Set default values to the smallest DDR we have in capricorn modules
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* Use it in case the system controller would return an error
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*/
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#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
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#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
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#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
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#endif /* __IMX8X_CAPRICORN_H */
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