forked from OERV-BSP/u-boot
f5e968a28e
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236 - Add support for STM32 TIMERS and STM32 PWM on STM32MP25 - Add STM32MP13xx SPL and OpTee-OS start support - Fix header misuse in stm32 reset drivers - Fix STMicroelectronics spelling - Fix clk-stm32h7 wrong macros used in register read - Fix PRE_CON_BUF_ADDR on STM32MP13 - Fix clock identifier passed to struct scmi_clk_parent_set_in - Fix stm32 reset for STM32F4/F7 and H7 - Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig - Add STM32MP23 SoC and stm32mp235f-dk board support
46 lines
1.4 KiB
Plaintext
46 lines
1.4 KiB
Plaintext
#include <configs/stm32mp_dhsom.config>
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# CONFIG_ARMV7_VIRT is not set
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# CONFIG_BINMAN_FDT is not set
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_BOARD_SIZE_LIMIT=1441792
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CONFIG_BOOTCOUNT_BOOTLIMIT=3
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CONFIG_BOOTDELAY=1
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CONFIG_BOOTRETRY=y
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CONFIG_RESET_TO_RETRY=y
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CONFIG_BOOT_RETRY_TIME=-1
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CONFIG_CMD_ADC=y
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CONFIG_CMD_REMOTEPROC=y
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CONFIG_CMD_STBOARD=y
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CONFIG_CMD_STM32PROG_OTP=y
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CONFIG_CONSOLE_MUX=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
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CONFIG_DM_HWSPINLOCK=y
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CONFIG_HAS_BOARD_SIZE_LIMIT=y
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CONFIG_HWSPINLOCK_STM32=y
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CONFIG_KS8851_MLL=y
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CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers"
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CONFIG_PHY_ANEG_TIMEOUT=20000
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CONFIG_PINCTRL_STMFX=y
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CONFIG_REMOTEPROC_STM32_COPRO=y
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CONFIG_SERVERIP="192.168.1.1"
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CONFIG_SF_DEFAULT_SPEED=50000000
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CONFIG_STM32_ADC=y
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CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
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CONFIG_SYS_MALLOC_F_LEN=0x3000
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CONFIG_SYS_PBSIZE=1050
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CONFIG_PREBOOT="run dh_preboot"
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
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CONFIG_TARGET_DH_STM32MP1_PDK2=y
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CONFIG_USE_SERVERIP=y
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CONFIG_WATCHDOG_AUTOSTART=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
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CONFIG_SPL_TEXT_BASE=0x2FFC2500
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CONFIG_SPL_BLOCK_CACHE=y
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CONFIG_SPL_MMC=y
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