forked from OERV-BSP/u-boot
5fe9ced355
Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
9 lines
151 B
Makefile
9 lines
151 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2025, Yao Zi <ziyao@disroot.org>
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obj-y += cache.o
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obj-y += cpu.o
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obj-y += dram.o
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obj-y += spl.o
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