forked from OERV-BSP/u-boot
39a6a2a8a2
DRAM init code, as per reverse engineering and matching against previous SoCs. As usual no real documentation, and the DRAM controller is the usual mixture of close-to-previous IP and new inventions. This version supports LPDDR4 for now only, as seen on the early boards. This needs improvements, but it can be done later. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>