board: spacemit-k3: Add i2c driver

board: spacemit-k3: Add reset driver to support other deivers
board: spacemit-k3: Add early timer support for k3
2026-05-30 15:28:19 +08:00 · 2026-05-30 15:28:19 +08:00 · 2026-05-30 15:28:14 +08:00 · 2026-05-30 14:34:48 +08:00
18 changed files with 1457 additions and 5 deletions
@@ -23,6 +23,7 @@ config SPACEMIT_K3
 	imply SPL_PINCTRL
 	imply PINCTRL_SINGLE
 	imply SYS_NS16550
+    imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE

 if SPACEMIT_K3

@@ -32,6 +32,11 @@
 			d-cache-sets = <256>;
 			next-level-cache = <&cluster0_l2_cache>;
 			mmu-type = "riscv,sv39";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
 		};

 		cluster0_l2_cache: l2-cache0 {
@@ -43,4 +43,12 @@
            K3_PADCONF(94, MUX_MODE3, (PULL_UP | PAD_DS8))  /* rx */
        >;
    };
+
+   	pinctrl_i2c2_1: i2c2_1_grp {
+        bootph-all;
+		pinctrl-single,pins = <
+			K3_PADCONF(46, MUX_MODE5, (PULL_UP | PAD_DS0)) /* i2c2_scl */
+			K3_PADCONF(47, MUX_MODE5, (PULL_UP | PAD_DS0)) /* i2c2_sda */
+		>;
+	};
 };
@@ -37,6 +37,20 @@
 		spi-max-frequency = <26500000>;
 		m25p,fast-read;
 		broken-flash-reset;
+	};
+};
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	status = "okay";
+
+	eeprom@50{
+		bootph-all;
+		compatible = "atmel,24c02";
+		reg = <0x50>;
 		status = "okay";
 	};
 };
@@ -7,6 +7,7 @@

 #include "k3-cpus.dtsi"
 #include <dt-bindings/clock/spacemit-k3-clock.h>
+#include <dt-bindings/reset/reset-spacemit-k3.h>

 / {
 	#address-cells = <2>;
@@ -16,6 +17,7 @@

 	aliases {
 		serial0 = &serial0;
+		i2c2 = &i2c2;
 	};

 	clocks {
@@ -114,6 +116,30 @@
 			};
 		};

+        clint: timer@e081c000 {
+            compatible = "spacemit,k3-clint", "sifive,clint0";
+            reg = <0x0 0xe081c000 0x0 0x4000>;
+            bootph-pre-ram;
+            interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+        };
+
+        reset: reset-controller@d4050000 {
+            bootph-all;
+           	compatible = "spacemit,k3-reset";
+           	reg = <0x0 0xd4050000 0x0 0x209c>,
+              		<0x0 0xd4282800 0x0 0x400>,
+              		<0x0 0xd4015000 0x0 0x1000>,
+              		<0x0 0xd4090000 0x0 0x1000>,
+              		<0x0 0xd4282c00 0x0 0x400>,
+              		<0x0 0xd8440000 0x0 0x98>,
+              		<0x0 0xc0000000 0x0 0x4280>,
+              		<0x0 0xf0610000 0x0 0x20>,
+              		<0x0 0xc0880000 0x0 0xd100>;
+           	reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2","rcpu";
+           	#reset-cells = <1>;
+           	status = "okay";
+        };
+
 		serial0: serial@d4017000 {
 			bootph-all;
 			compatible = "intel,xscale-uart";
@@ -137,6 +163,19 @@
 			clocks = <&ccu CLK_QSPI>, <&ccu CLK_QSPI_BUS>;
 			status = "disabled";
 		};
+
+		i2c2: twsi2@d4012000 {
+		    bootph-all;
+			compatible = "spacemit,i2c";
+			reg = <0x0 0xd4012000 0x0 0x38>;
+			clocks = <&ccu CLK_TWSI2>, <&ccu CLK_TWSI2_BUS>;
+			clock-names = "i2c2_en", "i2c2";
+			resets = <&reset RESET_TWSI2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};

 };
@@ -4,3 +4,16 @@ CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
 CONFIG_SPL_CLK=y
 CONFIG_SPACEMIT_K3_CCU=y
+CONFIG_TIMER_EARLY=y
+CONFIG_RISCV_TIMER=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_RESET_SPACEMIT_K3=y
+CONFIG_SPL_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_SPACEMIT=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
@@ -32,7 +32,10 @@ static SPACEMIT_CCU_PLLA(pll2, "pll2", &pll2_rate_tbl, ARRAY_SIZE(pll2_rate_tbl)
 	BASE_TYPE_APBS, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3,
 	MPMU_POSR, POSR_PLL2_LOCK, 1,
 	0);
-
+static SPACEMIT_CCU_GATE_FACTOR(pll1_d4, "pll1_d4", "pll1_2457p6_vco",
+	BASE_TYPE_APBS, APBS_PLL1_SWCR2,
+	BIT(3), BIT(3), 0x0,
+	4, 1, 0);
 static SPACEMIT_CCU_GATE_FACTOR(pll1_d5, "pll1_d5", "pll1_2457p6_vco",
 	BASE_TYPE_APBS, APBS_PLL1_SWCR2,
 	BIT(4), BIT(4), 0x0,
@@ -73,6 +76,27 @@ static SPACEMIT_CCU_GATE_FACTOR(pll1_d10_245p76, "pll1_d10_245p76", "pll1_d5",
 	BIT(18), BIT(18), 0x0,
 	2, 1, 0);

+static SPACEMIT_CCU_GATE_FACTOR(pll1_d24_102p4, "pll1_d24_102p4", "pll1_d8",
+	BASE_TYPE_MPMU, MPMU_ACGR,
+	BIT(12), BIT(12), 0x0,
+	3, 1, 0);
+static SPACEMIT_CCU_GATE_FACTOR(pll1_d96_25p6, "pll1_d96_25p6", "pll1_d8",
+	BASE_TYPE_MPMU, MPMU_ACGR,
+	BIT(4), BIT(4), 0x0,
+	12, 1, 0);
+
+
+static SPACEMIT_CCU_GATE_FACTOR(pll1_d78_31p5, "pll1_d78_31p5", "pll1_d4",
+	BASE_TYPE_MPMU, MPMU_ACGR,
+	BIT(6), BIT(6), 0x0,
+	39, 2, 0);
+static SPACEMIT_CCU_GATE_FACTOR(pll1_d48_51p2, "pll1_d48_51p2", "pll1_d8",
+	BASE_TYPE_MPMU, MPMU_ACGR,
+	BIT(7), BIT(7), 0x0,
+	6, 1, 0);
+static SPACEMIT_CCU_FACTOR(pll1_d40_61p44, "pll1_d40_61p44", "pll1_d8_307p2",
+	5, 1);
+
 static const char * const qspi_parent_names[] = {
 	"pll1_d6_409p6", "pll2_d8", "pll1_d8_307p2", "pll1_d10_245p76",
 	"clk_dummy", "pll1_dx", "pll1_d5_491p52", "clk_dummy"
@@ -89,21 +113,59 @@ static SPACEMIT_CCU_GATE(qspi_bus_clk, "qspi_bus_clk", "clk_dummy",
 	BIT(3), BIT(3), 0x0,
 	0);

+static const char *twsi_parent_names[] = {
+		"pll1_d78_31p5", "pll1_d48_51p2", "pll1_d40_61p44"
+};
+
+static SPACEMIT_CCU_MUX_GATE(twsi2_clk, "twsi2_clk", twsi_parent_names,
+	BASE_TYPE_APBC, APBC_TWSI2_CLK_RST,
+	4, 3, 0x3, 0x3, 0x0,
+	0);
+
+
+static const char * const apb_parent_names[] = {
+	"pll1_d96_25p6", "pll1_d48_51p2",
+	"pll1_d96_25p6", "pll1_d24_102p4"
+};
+
+static SPACEMIT_CCU_MUX(apb_clk, "apb_clk", apb_parent_names,
+  	BASE_TYPE_MPMU, MPMU_APBCSCR,
+  	0, 2, 0);
+
+static SPACEMIT_CCU_GATE(twsi2_bus_clk, "twsi2_bus_clk", "apb_clk",
+  	BASE_TYPE_APBC, APBC_TWSI2_CLK_RST,
+  	BIT(0), BIT(0), 0x0,
+  	0);
+
+
+
+
 static struct spacemit_clk_table spacemit_k3_clks = {
 	.clks	= {
 		[CLK_PLL1_2457P6]	= &pll1_2457p6_vco.common.clk,
 		[CLK_PLL2]		= &pll2.common.clk,
+		[CLK_PLL1_D4]		= &pll1_d4.common.clk,
 		[CLK_PLL1_D5]		= &pll1_d5.common.clk,
 		[CLK_PLL1_D6]		= &pll1_d6.common.clk,
 		[CLK_PLL1_D8]		= &pll1_d8.common.clk,
 		[CLK_PLL1_DX]		= &pll1_dx.common.clk,
 		[CLK_PLL2_D8]		= &pll2_d8.common.clk,
+		[CLK_PLL1_31P5]		= &pll1_d78_31p5.common.clk,
+		[CLK_PLL1_51P2]	= &pll1_d48_51p2.common.clk,
+		[CLK_PLL1_61P44]	= &pll1_d40_61p44.common.clk,
+
+        [CLK_PLL1_102P4] = &pll1_d24_102p4.common.clk,
+        [CLK_PLL1_25P6]  = &pll1_d96_25p6.common.clk,
+        [CLK_APB]        = &apb_clk.common.clk,
+        [CLK_TWSI2_BUS]  = &twsi2_bus_clk.common.clk,
+
 		[CLK_PLL1_307P2]	= &pll1_d8_307p2.common.clk,
 		[CLK_PLL1_409P6]	= &pll1_d6_409p6.common.clk,
 		[CLK_PLL1_491]		= &pll1_d5_491p52.common.clk,
 		[CLK_PLL1_245P76]	= &pll1_d10_245p76.common.clk,
 		[CLK_QSPI]		= &qspi_clk.common.clk,
 		[CLK_QSPI_BUS]		= &qspi_bus_clk.common.clk,
+		[CLK_TWSI2]		= &twsi2_clk.common.clk,
 	},
 	.num = CLK_MAX_NO,
 };
@@ -223,7 +285,7 @@ int spacemit_ccu_probe(struct spacemit_ccu_clk *clk_info,
 		if (!clk)
 			continue;

-		if (i >= CLK_VCTCXO_24)
+		if (i >= CLK_VCTCXO_24 && i != CLK_TWSI2_BUS)
 			continue;

 		clk->id = i;
@@ -17,6 +17,9 @@
 #define POSR_PLL2_LOCK			BIT(25)
 #define MPMU_ACGR			0x1024

+#define MPMU_APBCSCR            0x1050
+#define APBC_TWSI2_CLK_RST      0x38
+
 #define APMU_QSPI_CLK_RES_CTRL		0x060

 #endif /* _CCU_SPACEMIT_K3_H_ */
@@ -817,6 +817,12 @@ config SYS_I2C_IHS
        help
          Support for gdsys IHS I2C driver on FPGA bus.

+config SYS_I2C_SPACEMIT
+        bool "SPACEMIT I2C driver"
+        depends on DM_I2C || TARGET_SPACEMIT_K3
+        help
+          Support for SPACEMIT I2C controllers.
+
 source "drivers/i2c/muxes/Kconfig"

 endif
@@ -58,5 +58,5 @@ obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
 obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
 obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o
 obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
-
+obj-$(CONFIG_$(SPL_)SYS_I2C_SPACEMIT) += spacemit_i2c.o
 obj-$(CONFIG_$(PHASE_)I2C_MUX) += muxes/
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Spacemit
+ */
+
+#include <dm.h>
+#include <reset.h>
+#include <clk.h>
+#include <i2c.h>
+#include <log.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include "spacemit_i2c.h"
+
+/* All transfers are described by this data structure */
+struct spacemit_i2c_msg {
+	u8 condition;
+	u8 acknack;
+	u8 direction;
+	u8 data;
+};
+
+struct spacemit_i2c {
+	u32 icr;
+	u32 isr;
+	u32 isar;
+	u32 idbr;
+	u32 ilcr;
+	u32 iwcr;
+	u32 irst_cyc;
+	u32 ibmr;
+};
+
+/*
+ * i2c_reset: - reset the host controller
+ *
+ */
+static void i2c_reset(struct spacemit_i2c *base, bool sda_glitch_nofix)
+{
+	u32 icr_mode;
+
+	/* Save bus mode (standard or fast speed) for later use */
+	icr_mode = readl(&base->icr) & ICR_MODE_MASK;
+	writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
+	writel(readl(&base->icr) | ICR_UR, &base->icr);	  /* reset the unit */
+	udelay(100);
+	writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
+
+#ifdef CONFIG_SYS_I2C_SLAVE
+	writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
+#else
+	writel(0x00, &base->isar); /* set our slave address */
+#endif
+	/* set control reg values */
+	writel(I2C_ICR_INIT | icr_mode, &base->icr);
+	writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
+	if (sda_glitch_nofix)
+		writel(readl(&base->irst_cyc) | IRCR_SDA_GLITCH_NOFIX,
+		       &base->irst_cyc);
+	writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
+	udelay(1e0);
+}
+
+/*
+ * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
+ *	                  are set and cleared
+ *
+ * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
+ */
+static int i2c_isr_set_cleared(struct spacemit_i2c *base, unsigned long set_mask,
+			       unsigned long cleared_mask)
+{
+	int timeout = 1000, isr;
+
+	do {
+		isr = readl(&base->isr);
+		/* udelay(10); */
+		/* this delay time can't exceed the watchog timeout period */
+		__udelay(10);
+		if (timeout-- < 0)
+			return 0;
+	} while (((isr & set_mask) != set_mask)
+		|| ((isr & cleared_mask) != 0));
+
+	return 1;
+}
+
+/*
+ * i2c_transfer: - Transfer one byte over the i2c bus
+ *
+ * This function can tranfer a byte over the i2c bus in both directions.
+ * It is used by the public API functions.
+ *
+ * @return:  0: transfer successful
+ *          -1: message is empty
+ *          -2: transmit timeout
+ *          -3: ACK missing
+ *          -4: receive timeout
+ *          -5: illegal parameters
+ *          -6: bus is busy and couldn't be aquired
+ */
+static int i2c_transfer(struct spacemit_i2c *base, struct spacemit_i2c_msg *msg,
+			bool sda_glitch_nofix)
+{
+	int ret;
+
+	if (!msg)
+		goto transfer_error_msg_empty;
+
+	switch (msg->direction) {
+	case I2C_WRITE:
+		/* check if bus is not busy */
+		if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
+			goto transfer_error_bus_busy;
+
+		/* start transmission */
+		writel(readl(&base->icr) & ~ICR_START, &base->icr);
+		writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
+		writel(msg->data, &base->idbr);
+		if (msg->condition == I2C_COND_START)
+			writel(readl(&base->icr) | ICR_START, &base->icr);
+		if (msg->condition == I2C_COND_STOP)
+			writel(readl(&base->icr) | ICR_STOP, &base->icr);
+		if (msg->acknack == I2C_ACKNAK_SENDNAK)
+			writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
+		if (msg->acknack == I2C_ACKNAK_SENDACK)
+			writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
+		writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
+		writel(readl(&base->icr) | ICR_TB, &base->icr);
+
+		/* transmit register empty? */
+		if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
+			goto transfer_error_transmit_timeout;
+
+		/* clear 'transmit empty' state */
+		writel(readl(&base->isr) | ISR_ITE, &base->isr);
+
+		/* wait for ACK from slave */
+		if (msg->acknack == I2C_ACKNAK_WAITACK)
+			if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
+				goto transfer_error_ack_missing;
+		break;
+
+	case I2C_READ:
+
+		/* check if bus is not busy */
+		if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
+			goto transfer_error_bus_busy;
+
+		/* start receive */
+		writel(readl(&base->icr) & ~ICR_START, &base->icr);
+		writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
+		if (msg->condition == I2C_COND_START)
+			writel(readl(&base->icr) | ICR_START, &base->icr);
+		if (msg->condition == I2C_COND_STOP)
+			writel(readl(&base->icr) | ICR_STOP, &base->icr);
+		if (msg->acknack == I2C_ACKNAK_SENDNAK)
+			writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
+		if (msg->acknack == I2C_ACKNAK_SENDACK)
+			writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
+		writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
+		writel(readl(&base->icr) | ICR_TB, &base->icr);
+
+		/* receive register full? */
+		if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
+			goto transfer_error_receive_timeout;
+
+		msg->data = readl(&base->idbr);
+
+		/* clear 'receive empty' state */
+		writel(readl(&base->isr) | ISR_IRF, &base->isr);
+		break;
+	default:
+		goto transfer_error_illegal_param;
+	}
+
+	return 0;
+
+transfer_error_msg_empty:
+	debug("i2c_transfer: error: 'msg' is empty\n");
+	ret = -1;
+	goto i2c_transfer_finish;
+
+transfer_error_transmit_timeout:
+	debug("i2c_transfer: error: transmit timeout\n");
+	ret = -2;
+	goto i2c_transfer_finish;
+
+transfer_error_ack_missing:
+	debug("i2c_transfer: error: ACK missing\n");
+	ret = -3;
+	goto i2c_transfer_finish;
+
+transfer_error_receive_timeout:
+	debug("i2c_transfer: error: receive timeout\n");
+	ret = -4;
+	goto i2c_transfer_finish;
+
+transfer_error_illegal_param:
+	debug("i2c_transfer: error: illegal parameters\n");
+	ret = -5;
+	goto i2c_transfer_finish;
+
+transfer_error_bus_busy:
+	debug("i2c_transfer: error: bus is busy\n");
+	ret = -6;
+	goto i2c_transfer_finish;
+
+i2c_transfer_finish:
+	debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
+	i2c_reset(base, sda_glitch_nofix);
+	return ret;
+}
+
+static int __i2c_read(struct spacemit_i2c *base, uchar chip, u8 *addr, int alen,
+		      uchar *buffer, int len, bool sda_glitch_nofix)
+{
+	struct spacemit_i2c_msg msg;
+
+	debug("i2c_read(chip=0x%02x, len=0x%02x)\n", chip, len);
+
+	if (len == 0) {
+		pr_err("reading zero byte is invalid\n");
+		return -EINVAL;
+	}
+
+	i2c_reset(base, sda_glitch_nofix);
+
+	/* dummy chip address write */
+	debug("i2c_read: dummy chip address write\n");
+	msg.condition = I2C_COND_START;
+	msg.acknack   = I2C_ACKNAK_WAITACK;
+	msg.direction = I2C_WRITE;
+	msg.data = (chip << 1);
+	msg.data &= 0xFE;
+	if (i2c_transfer(base, &msg, sda_glitch_nofix))
+		return -1;
+
+	/*
+	 * send memory address bytes;
+	 * alen defines how much bytes we have to send.
+	 */
+	while (--alen >= 0) {
+		debug("i2c_read: send address byte %02x (alen=%d)\n",
+		      *addr, alen);
+		msg.condition = I2C_COND_NORMAL;
+		msg.acknack   = I2C_ACKNAK_WAITACK;
+		msg.direction = I2C_WRITE;
+		msg.data      = addr[alen];
+		if (i2c_transfer(base, &msg, sda_glitch_nofix))
+			return -1;
+	}
+
+	/* start read sequence */
+	debug("i2c_read: start read sequence\n");
+	msg.condition = I2C_COND_START;
+	msg.acknack   = I2C_ACKNAK_WAITACK;
+	msg.direction = I2C_WRITE;
+	msg.data      = (chip << 1);
+	msg.data     |= 0x01;
+	if (i2c_transfer(base, &msg, sda_glitch_nofix))
+		return -1;
+
+	/* read bytes; send NACK at last byte */
+	while (len--) {
+		if (len == 0) {
+			msg.condition = I2C_COND_STOP;
+			msg.acknack   = I2C_ACKNAK_SENDNAK;
+		} else {
+			msg.condition = I2C_COND_NORMAL;
+			msg.acknack   = I2C_ACKNAK_SENDACK;
+		}
+
+		msg.direction = I2C_READ;
+		msg.data      = 0x00;
+		if (i2c_transfer(base, &msg, sda_glitch_nofix))
+			return -1;
+
+		*buffer = msg.data;
+		debug("i2c_read: reading byte (%p)=0x%02x\n",
+		      buffer, *buffer);
+		buffer++;
+	}
+
+	i2c_reset(base, sda_glitch_nofix);
+
+	return 0;
+}
+
+static int __i2c_write(struct spacemit_i2c *base, uchar chip, u8 *addr, int alen,
+		       uchar *buffer, int len, bool sda_glitch_nofix)
+{
+	struct spacemit_i2c_msg msg;
+
+	debug("i2c_write(chip=0x%02x, len=0x%02x)\n", chip, len);
+
+	i2c_reset(base, sda_glitch_nofix);
+
+	/* chip address write */
+	debug("i2c_write: chip address write\n");
+	msg.condition = I2C_COND_START;
+	msg.acknack   = I2C_ACKNAK_WAITACK;
+	msg.direction = I2C_WRITE;
+	msg.data = (chip << 1);
+	msg.data &= 0xFE;
+	if (i2c_transfer(base, &msg, sda_glitch_nofix))
+		return -1;
+
+	/*
+	 * send memory address bytes;
+	 * alen defines how much bytes we have to send.
+	 */
+	while (--alen >= 0) {
+		debug("i2c_read: send address byte %02x (alen=%d)\n",
+		      *addr, alen);
+		msg.condition = I2C_COND_NORMAL;
+		msg.acknack   = I2C_ACKNAK_WAITACK;
+		msg.direction = I2C_WRITE;
+		msg.data      = addr[alen];
+		if (i2c_transfer(base, &msg, sda_glitch_nofix))
+			return -1;
+	}
+
+	/* write bytes; send NACK at last byte */
+	while (len--) {
+		debug("i2c_write: writing byte (%p)=0x%02x\n",
+		      buffer, *buffer);
+
+		if (len == 0)
+			msg.condition = I2C_COND_STOP;
+		else
+			msg.condition = I2C_COND_NORMAL;
+
+		msg.acknack   = I2C_ACKNAK_WAITACK;
+		msg.direction = I2C_WRITE;
+		msg.data      = *(buffer++);
+
+		if (i2c_transfer(base, &msg, sda_glitch_nofix))
+			return -1;
+	}
+
+	i2c_reset(base, sda_glitch_nofix);
+
+	return 0;
+}
+
+
+struct spacemit_i2c_priv {
+	struct spacemit_i2c *base;
+	struct reset_ctl_bulk resets;
+#if CONFIG_IS_ENABLED(CLK)
+        struct clk clk_func;
+        struct clk clk_bus;
+#endif
+	u32 clk_rate;
+	bool sda_glitch_nofix;
+};
+
+static int spacemit_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	struct spacemit_i2c_priv *i2c = dev_get_priv(bus);
+	struct i2c_msg *dmsg, *omsg, dummy;
+
+	memset(&dummy, 0, sizeof(struct i2c_msg));
+
+	/*
+	 * We expect either two messages (one with an offset and one with the
+	 * actual data) or one message (just data or offset/data combined)
+	 */
+	if (nmsgs > 2 || nmsgs == 0) {
+		debug("%s: Only one or two messages are supported.", __func__);
+		return -1;
+	}
+
+	omsg = nmsgs == 1 ? &dummy : msg;
+	dmsg = nmsgs == 1 ? msg : msg + 1;
+
+	if (dmsg->flags & I2C_M_RD)
+		return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
+				  omsg->len, dmsg->buf, dmsg->len,
+				  i2c->sda_glitch_nofix);
+	else
+		return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
+				   omsg->len, dmsg->buf, dmsg->len,
+				   i2c->sda_glitch_nofix);
+}
+
+static int spacemit_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+	struct spacemit_i2c_priv *priv = dev_get_priv(bus);
+	u32 val;
+
+	if (speed > 100000)
+		val = ICR_FM;
+	else
+		val = ICR_SM;
+	clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
+
+	return 0;
+}
+
+static int spacemit_i2c_probe(struct udevice *bus)
+{
+	struct spacemit_i2c_priv *priv = dev_get_priv(bus);
+	int ret;
+
+	ret = reset_get_bulk(bus, &priv->resets);
+        ret = reset_deassert_bulk(&priv->resets);
+        if (ret){
+                debug("I2C probe: failed to reset \n");
+                return ret;
+        }
+
+#if CONFIG_IS_ENABLED(CLK)
+    ret = clk_get_by_name(bus, "i2c2_en", &priv->clk_func);
+    if (ret)
+    	return ret;
+
+    ret = clk_get_by_name(bus, "i2c2", &priv->clk_bus);
+    if (ret)
+    	return ret;
+
+    ret = clk_enable(&priv->clk_func);
+    if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+    	debug("I2C probe: failed to enable func clock\n");
+    	return ret;
+    }
+
+    ret = clk_enable(&priv->clk_bus);
+    if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+    	debug("I2C probe: failed to enable bus clock\n");
+    	return ret;
+    }
+
+#endif
+	priv->base = (void *)devfdt_get_addr_ptr(bus);
+	ret = dev_read_u32(bus, "clock-frequency", &priv->clk_rate);
+        if (ret) {
+                pr_info("Default to 100kHz\n");
+		/* default clock rate: 100k */
+                priv->clk_rate = 100000;
+        }
+
+	ret = spacemit_i2c_set_bus_speed(bus, priv->clk_rate);
+
+	priv->sda_glitch_nofix = dev_read_bool(bus, "spacemit,sda-glitch-nofix");
+
+	return 0;
+}
+
+static const struct dm_i2c_ops spacemit_i2c_ops = {
+	.xfer		= spacemit_i2c_xfer,
+	.set_bus_speed	= spacemit_i2c_set_bus_speed,
+};
+
+static const struct udevice_id spacemit_i2c_ids[] = {
+	{ .compatible = "spacemit,i2c" },
+	{ }
+};
+
+U_BOOT_DRIVER(i2c_spacemit) = {
+	.name	= "i2c_spacemit",
+	.id	= UCLASS_I2C,
+	.of_match = spacemit_i2c_ids,
+	.probe	= spacemit_i2c_probe,
+	.priv_auto = sizeof(struct spacemit_i2c_priv),
+	.ops	= &spacemit_i2c_ops,
+};
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Spacemit
+ */
+
+#ifndef _SPACEMIT_I2C_H_
+#define _SPACEMIT_I2C_H_
+extern void i2c_clk_enable(void);
+
+/* Shall the current transfer have a start/stop condition? */
+#define I2C_COND_NORMAL		0
+#define I2C_COND_START		1
+#define I2C_COND_STOP		2
+
+/* Shall the current transfer be ack/nacked or being waited for it? */
+#define I2C_ACKNAK_WAITACK	1
+#define I2C_ACKNAK_SENDACK	2
+#define I2C_ACKNAK_SENDNAK	4
+
+/* Specify who shall transfer the data (master or slave) */
+#define I2C_READ		0
+#define I2C_WRITE		1
+
+#if (CONFIG_SYS_I2C_SPEED == 400000)
+#define I2C_ICR_INIT	(ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
+		| ICR_SCLE)
+#else
+#define I2C_ICR_INIT	(ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#endif
+
+/* ----- Control register bits ---------------------------------------- */
+
+#define ICR_START	0x1		/* start bit */
+#define ICR_STOP	0x2		/* stop bit */
+#define ICR_ACKNAK	0x4		/* send ACK(0) or NAK(1) */
+#define ICR_TB		0x8		/* transfer byte bit */
+#define ICR_MA		BIT(12)  	/* master abort */
+#define ICR_SCLE	BIT(13)  	/* master clock enable, mona SCLEA */
+#define ICR_IUE		BIT(14) 	/* unit enable */
+#define ICR_GCD		BIT(21) 	/* general call disable */
+#define ICR_ITEIE	BIT(19)  	/* enable tx interrupts */
+#define ICR_IRFIE	BIT(20)  	/* enable rx interrupts, mona: DRFIE */
+#define ICR_BEIE	BIT(22)  	/* enable bus error ints */
+#define ICR_SSDIE	BIT(24)  	/* slave STOP detected int enable */
+#define ICR_ALDIE	BIT(18)		/* enable arbitration interrupt */
+#define ICR_SADIE	BIT(23)		/* slave address detected int enable */
+#define ICR_UR		BIT(10)		/* unit reset */
+#define ICR_SM		(0x0)		/* Standard Mode */
+#define ICR_FM		BIT(8)		/* Fast Mode */
+#define ICR_MODE_MASK	(0x300)		/* Mode mask */
+/* ----- Status register bits ----------------------------------------- */
+
+#define ISR_RWM		BIT(13)   	/* read/write mode */
+#define ISR_ACKNAK	BIT(14)   	/* ack/nak status */
+#define ISR_UB		BIT(15)   	/* unit busy */
+#define ISR_IBB		BIT(16)   	/* bus busy */
+#define ISR_SSD		BIT(24)   	/* slave stop detected */
+#define ISR_ALD		BIT(18)   	/* arbitration loss detected */
+#define ISR_ITE		BIT(19)   	/* tx buffer empty */
+#define ISR_IRF		BIT(20)   	/* rx buffer full */
+#define ISR_GCAD	BIT(21)		/* general call address detected */
+#define ISR_SAD		BIT(23)		/* slave address detected */
+#define ISR_BED		BIT(22)		/* bus error no ACK/NAK */
+
+/* ----- Reset cycle counter register bits -------------------------------- */
+
+#define IRCR_SDA_GLITCH_NOFIX	BIT(7)		/* bypass the SDA glitch fix */
+
+#define I2C_ISR_INIT	0x1FDE000
+
+#endif
@@ -252,5 +252,13 @@ config RESET_SPACEMIT_K1
 	  Support for SPACEMIT's K1 Reset system. Basic Assert/Deassert
 	  is supported.

+config RESET_SPACEMIT_K3
+	bool "Support for SPACEMIT's K3 Reset driver"
+	depends on DM_RESET
+	help
+	  Support for SPACEMIT's K3 Reset system. Basic Assert/Deassert
+	  is supported.
+
+
 source "drivers/reset/stm32/Kconfig"
 endmenu
@@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_AT91) += reset-at91.o
 obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o
 obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
 obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o
+obj-$(CONFIG_RESET_SPACEMIT_K3) += reset-spacemit-k3.o

 obj-$(CONFIG_ARCH_STM32) += stm32/
 obj-$(CONFIG_ARCH_STM32MP) += stm32/
@@ -0,0 +1,566 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Spacemit K3 reset controller driver
+ *
+ * Copyright (c) 2025, spacemit Corporation.
+ *
+ */
+
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/bitops.h>
+#include <dt-bindings/reset/reset-spacemit-k3.h>
+
+/* APBC register offset */
+#define APBC_UART0_CLK_RST      0x00
+#define APBC_UART2_CLK_RST      0x04
+#define APBC_GPIO_CLK_RST       0x08
+#define APBC_PWM0_CLK_RST       0x0c
+#define APBC_PWM1_CLK_RST       0x10
+#define APBC_PWM2_CLK_RST       0x14
+#define APBC_PWM3_CLK_RST       0x18
+#define APBC_TWSI8_CLK_RST      0x20
+#define APBC_UART3_CLK_RST      0x24
+#define APBC_RTC_CLK_RST        0x28
+#define APBC_TWSI0_CLK_RST      0x2c
+#define APBC_TWSI1_CLK_RST      0x30
+#define APBC_TIMERS0_CLK_RST    0x34
+#define APBC_TWSI2_CLK_RST      0x38
+#define APBC_AIB_CLK_RST        0x3c
+#define APBC_TWSI4_CLK_RST      0x40
+#define APBC_TIMERS1_CLK_RST    0x44
+#define APBC_ONEWIRE_CLK_RST    0x48
+#define APBC_TWSI5_CLK_RST      0x4c
+#define APBC_DRO_CLK_RST        0x58
+#define APBC_IR0_CLK_RST        0x5c
+#define APBC_IR1_CLK_RST        0x1c
+#define APBC_TWSI6_CLK_RST      0x60
+#define APBC_TSEN_CLK_RST       0x6c
+#define APBC_UART4_CLK_RST      0x70
+#define APBC_UART5_CLK_RST      0x74
+#define APBC_UART6_CLK_RST      0x78
+#define APBC_SSP3_CLK_RST       0x7c
+#define APBC_SSPA0_CLK_RST      0x80
+#define APBC_SSPA1_CLK_RST      0x84
+#define APBC_SSPA2_CLK_RST      0x88
+#define APBC_SSPA3_CLK_RST      0x8c
+#define APBC_IPC_AP2AUD_CLK_RST 0x90
+#define APBC_UART7_CLK_RST      0x94
+#define APBC_UART8_CLK_RST      0x98
+#define APBC_UART9_CLK_RST      0x9c
+#define APBC_CAN0_CLK_RST       0xa0
+#define APBC_CAN1_CLK_RST       0xa4
+#define APBC_PWM4_CLK_RST       0xa8
+#define APBC_PWM5_CLK_RST       0xac
+#define APBC_PWM6_CLK_RST       0xb0
+#define APBC_PWM7_CLK_RST       0xb4
+#define APBC_PWM8_CLK_RST       0xb8
+#define APBC_PWM9_CLK_RST       0xbc
+#define APBC_PWM10_CLK_RST      0xc0
+#define APBC_PWM11_CLK_RST      0xc4
+#define APBC_PWM12_CLK_RST      0xc8
+#define APBC_PWM13_CLK_RST      0xcc
+#define APBC_PWM14_CLK_RST      0xd0
+#define APBC_PWM15_CLK_RST      0xd4
+#define APBC_PWM16_CLK_RST      0xd8
+#define APBC_PWM17_CLK_RST      0xdc
+#define APBC_PWM18_CLK_RST      0xe0
+#define APBC_PWM19_CLK_RST      0xe4
+#define APBC_TIMERS2_CLK_RST    0x11c
+#define APBC_TIMERS3_CLK_RST    0x120
+#define APBC_TIMERS4_CLK_RST    0x124
+#define APBC_TIMERS5_CLK_RST    0x128
+#define APBC_TIMERS6_CLK_RST    0x12c
+#define APBC_TIMERS7_CLK_RST    0x130
+#define APBC_CAN2_CLK_RST       0x148
+#define APBC_CAN3_CLK_RST       0x14c
+#define APBC_CAN4_CLK_RST       0x150
+#define APBC_UART10_CLK_RST     0x154
+#define APBC_SSP0_CLK_RST       0x158
+#define APBC_SSP1_CLK_RST       0x15c
+#define APBC_SSPA4_CLK_RST      0x160
+#define APBC_SSPA5_CLK_RST      0x164
+/* end of APBC register offset */
+
+/* MPMU register offset */
+#define MPMU_WDTPCR             0x200
+#define MPMU_RIPCCR             0x210
+/* end of MPMU register offset */
+
+/* APMU register offset */
+#define APMU_CSI_CCIC2_CLK_RES_CTRL     0x24
+#define APMU_ISP_CLK_RES_CTRL           0x38
+#define APMU_LCD_CLK_RES_CTRL1          0x44
+#define APMU_LCD_CLK_RES_CTRL2          0x4c
+#define APMU_CCIC_CLK_RES_CTRL          0x50
+#define APMU_SDH0_CLK_RES_CTRL          0x54
+#define APMU_SDH1_CLK_RES_CTRL          0x58
+#define APMU_USB_CLK_RES_CTRL           0x5c
+#define APMU_QSPI_CLK_RES_CTRL          0x60
+#define APMU_DMA_CLK_RES_CTRL           0x64
+#define APMU_AES_CLK_RES_CTRL           0x68
+#define APMU_MCB_CLK_RES_CTRL           0x6c
+#define APMU_VPU_CLK_RES_CTRL           0xa4
+#define APMU_DTC_CLK_RES_CTRL           0xac
+#define APMU_GPU_CLK_RES_CTRL           0xcc
+#define APMU_SDH2_CLK_RES_CTRL          0xe0
+#define APMU_PMUA_MC_CTRL               0xe8
+#define APMU_PMU_CC2_AP                 0x100
+#define APMU_UCIE_CTRL                  0x11c
+#define APMU_AUDIO_CLK_RES_CTRL         0x14c
+#define APMU_LCD_CLK_RES_CTRL3          0x26C
+#define APMU_UFS_CLK_RES_CTRL           0x268
+#define APMU_LCD_CLK_RES_CTRL4          0x270
+#define APMU_LCD_CLK_RES_CTRL5          0x274
+#define APMU_LCD_EDP_CTRL               0x23c
+#define APMU_PCIE_CLK_RES_CTRL_PORTA    0x1F0
+#define APMU_PCIE_CLK_RES_CTRL_PORTB    0x1D0
+#define APMU_PCIE_CLK_RES_CTRL_PORTC    0x1C8
+#define APMU_PCIE_CLK_RES_CTRL_PORTD    0x1E0
+#define APMU_PCIE_CLK_RES_CTRL_PORTE    0x1E8
+#define APMU_EMAC0_CLK_RES_CTRL         0x3e4
+#define APMU_EMAC1_CLK_RES_CTRL         0x3ec
+#define APMU_EMAC2_CLK_RES_CTRL         0x248
+#define APMU_ESPI_CLK_RES_CTRL          0x240
+/* end of APMU register offset */
+
+/* CIUDRAGON register offset */
+#define DCIU_DMASYS_S0_RSTN     0x204
+#define DCIU_DMASYS_S1_RSTN     0x208
+#define DCIU_DMASYS_A0_RSTN     0x20C
+#define DCIU_DMASYS_A1_RSTN     0x210
+#define DCIU_DMASYS_A2_RSTN     0x214
+#define DCIU_DMASYS_A3_RSTN     0x218
+#define DCIU_DMASYS_A4_RSTN     0x21C
+#define DCIU_DMASYS_A5_RSTN     0x220
+#define DCIU_DMASYS_A6_RSTN     0x224
+#define DCIU_DMASYS_A7_RSTN     0x228
+#define DCIU_DMASYS_RSTN        0x22C
+#define DCIU_DMASYS_SDMA_RSTN   0x230
+/* end of CIUDRAGON register offset */
+
+/* APBC2 register offset */
+#define APBC2_UART1_CLK_RST     0x00
+#define APBC2_SSP2_CLK_RST      0x04
+#define APBC2_TWSI3_CLK_RST     0x08
+#define APBC2_RTC_CLK_RST       0x0c
+#define APBC2_TIMERS_CLK_RST    0x10
+#define APBC2_JTAG_SW_CLK_RST   0x18
+#define APBC2_GPIO_CLK_RST      0x1c
+/* end of APBC2 register offset */
+
+/* RCPU register offset */
+//0xc088c000
+#define RCPU5_CLK_RST_OFFSET    0xC000
+#define RCPU5_RT24_CORE0_SW_RESET    (0xCC + RCPU5_CLK_RST_OFFSET)
+#define RCPU5_RT24_CORE1_SW_RESET    (0xD0 + RCPU5_CLK_RST_OFFSET)
+/* end of RCPU register offset */
+
+enum spacemit_reset_base_type {
+	RST_BASE_TYPE_MPMU       = 0,
+	RST_BASE_TYPE_APMU       = 1,
+	RST_BASE_TYPE_APBC       = 2,
+	RST_BASE_TYPE_APBS       = 3,
+	RST_BASE_TYPE_CIU        = 4,
+	RST_BASE_TYPE_DCIU       = 5,
+	RST_BASE_TYPE_DDRC       = 6,
+	RST_BASE_TYPE_APBC2      = 7,
+	RST_BASE_TYPE_RCPU       = 8,
+};
+
+struct spacemit_reset_signal {
+	u32 offset;
+	u32 mask;
+	u32 deassert_val;
+	u32 assert_val;
+	enum spacemit_reset_base_type type;
+};
+
+struct spacemit_reset {
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+	void __iomem *apbs_base;
+	void __iomem *ciu_base;
+	void __iomem *dciu_base;
+	void __iomem *ddrc_base;
+	void __iomem *apbc2_base;
+	void __iomem *rcpu_base;
+	const struct spacemit_reset_signal *signals;
+};
+
+struct spacemit_reset k3_reset_controller;
+
+static const struct spacemit_reset_signal
+	k3_reset_signals[RESET_NUMBER] = {
+	//APBC
+	[RESET_UART0]   = { APBC_UART0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART2]   = { APBC_UART2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART3]   = { APBC_UART3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART4]   = { APBC_UART4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART5]   = { APBC_UART5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART6]   = { APBC_UART6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART7]   = { APBC_UART7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART8]   = { APBC_UART8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART9]   = { APBC_UART9_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART10]  = { APBC_UART10_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_GPIO]    = { APBC_GPIO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM0]    = { APBC_PWM0_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM1]    = { APBC_PWM1_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM2]    = { APBC_PWM2_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM3]    = { APBC_PWM3_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM4]    = { APBC_PWM4_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM5]    = { APBC_PWM5_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM6]    = { APBC_PWM6_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM7]    = { APBC_PWM7_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM8]    = { APBC_PWM8_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM9]    = { APBC_PWM9_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM10]   = { APBC_PWM10_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM11]   = { APBC_PWM11_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM12]   = { APBC_PWM12_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM13]   = { APBC_PWM13_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM14]   = { APBC_PWM14_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM15]   = { APBC_PWM15_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM16]   = { APBC_PWM16_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM17]   = { APBC_PWM17_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM18]   = { APBC_PWM18_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_PWM19]   = { APBC_PWM19_CLK_RST, BIT(2)|BIT(0), BIT(0), BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_SPI0]    = { APBC_SSP0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_SPI1]    = { APBC_SSP1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_SPI3]    = { APBC_SSP3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_RTC]     = { APBC_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI0]   = { APBC_TWSI0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI1]   = { APBC_TWSI1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI2]   = { APBC_TWSI2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI4]   = { APBC_TWSI4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI5]   = { APBC_TWSI5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI6]   = { APBC_TWSI6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI8]   = { APBC_TWSI8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS0] = { APBC_TIMERS0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS1] = { APBC_TIMERS1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS2] = { APBC_TIMERS2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS3] = { APBC_TIMERS3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS4] = { APBC_TIMERS4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS5] = { APBC_TIMERS5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS6] = { APBC_TIMERS6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS7] = { APBC_TIMERS7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_AIB]     = { APBC_AIB_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_ONEWIRE] = { APBC_ONEWIRE_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_I2S0]    = { APBC_SSPA0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_I2S1]    = { APBC_SSPA1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_I2S2]    = { APBC_SSPA2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_I2S3]    = { APBC_SSPA3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_I2S4]    = { APBC_SSPA4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_I2S5]    = { APBC_SSPA5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_DRO]     = { APBC_DRO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_IR0]     = { APBC_IR0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_IR1]     = { APBC_IR1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TSEN]    = { APBC_TSEN_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_IPC_AP2AUD]   = { APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_CAN0]    = { APBC_CAN0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_CAN1]    = { APBC_CAN1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_CAN2]    = { APBC_CAN2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_CAN3]    = { APBC_CAN3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_CAN4]    = { APBC_CAN4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	//MPMU
+	[RESET_WDT]     = { MPMU_WDTPCR, BIT(2), 0, BIT(2), RST_BASE_TYPE_MPMU },
+	[RESET_RIPC]    = { MPMU_RIPCCR, BIT(2), 0, BIT(2), RST_BASE_TYPE_MPMU },
+	//APMU
+	[RESET_CSI]         = { APMU_CSI_CCIC2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC2_PHY]   = { APMU_CSI_CCIC2_CLK_RES_CTRL, BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC3_PHY]   = { APMU_CSI_CCIC2_CLK_RES_CTRL, BIT(29), BIT(29), 0, RST_BASE_TYPE_APMU },
+	[RESET_ISP_CIBUS]   = { APMU_ISP_CLK_RES_CTRL, BIT(16), BIT(16), 0, RST_BASE_TYPE_APMU },
+	[RESET_DSI_ESC]     = { APMU_LCD_CLK_RES_CTRL1, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD]         = { APMU_LCD_CLK_RES_CTRL1, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_V2D]         = { APMU_LCD_CLK_RES_CTRL1, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD_MCLK]    = { APMU_LCD_CLK_RES_CTRL2, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD_DSCCLK]  = { APMU_LCD_CLK_RES_CTRL2, BIT(15), BIT(15), 0, RST_BASE_TYPE_APMU },
+	[RESET_SC2_HCLK]    = { APMU_CCIC_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC_4X]     = { APMU_CCIC_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC1_PHY]   = { APMU_CCIC_CLK_RES_CTRL, BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH_AXI]     = { APMU_SDH0_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH0]        = { APMU_SDH0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH1]	    = { APMU_SDH1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH2]        = { APMU_SDH2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB2]	    = { APMU_USB_CLK_RES_CTRL, BIT(0)|BIT(2)|BIT(3), BIT(0)|BIT(2)|BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB3_PORTA]  = { APMU_USB_CLK_RES_CTRL, BIT(5)|BIT(6)|BIT(7), BIT(5)|BIT(6)|BIT(7), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB3_PORTB]  = { APMU_USB_CLK_RES_CTRL, BIT(9)|BIT(10)|BIT(11), BIT(9)|BIT(10)|BIT(11), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB3_PORTC]  = { APMU_USB_CLK_RES_CTRL, BIT(13)|BIT(14)|BIT(15), BIT(13)|BIT(14)|BIT(15), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB3_PORTD]  = { APMU_USB_CLK_RES_CTRL, BIT(17)|BIT(18)|BIT(19), BIT(17)|BIT(18)|BIT(19), 0, RST_BASE_TYPE_APMU },
+	[RESET_QSPI]        = { APMU_QSPI_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_QSPI_BUS]    = { APMU_QSPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_DMA]         = { APMU_DMA_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_AES_WTM]     = { APMU_AES_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_MCB_DCLK]    = { APMU_MCB_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_MCB_ACLK]    = { APMU_MCB_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_VPU]         = { APMU_VPU_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_DTC]         = { APMU_DTC_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_GPU]         = { APMU_GPU_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_MC]          = { APMU_PMUA_MC_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_CPU0_POP]    = { APMU_PMU_CC2_AP, BIT(0), 0, BIT(0), RST_BASE_TYPE_APMU },
+	[RESET_CPU0_SW]     = { APMU_PMU_CC2_AP, BIT(1), 0, BIT(1), RST_BASE_TYPE_APMU },
+	[RESET_CPU1_POP]    = { APMU_PMU_CC2_AP, BIT(3), 0, BIT(3), RST_BASE_TYPE_APMU },
+	[RESET_CPU1_SW]     = { APMU_PMU_CC2_AP, BIT(4), 0, BIT(4), RST_BASE_TYPE_APMU },
+	[RESET_CPU2_POP]    = { APMU_PMU_CC2_AP, BIT(6), 0, BIT(6), RST_BASE_TYPE_APMU },
+	[RESET_CPU2_SW]     = { APMU_PMU_CC2_AP, BIT(7), 0, BIT(7), RST_BASE_TYPE_APMU },
+	[RESET_CPU3_POP]    = { APMU_PMU_CC2_AP, BIT(9), 0, BIT(9), RST_BASE_TYPE_APMU },
+	[RESET_CPU3_SW]     = { APMU_PMU_CC2_AP, BIT(10), 0, BIT(10), RST_BASE_TYPE_APMU },
+	[RESET_C0_MPSUB_SW] = { APMU_PMU_CC2_AP, BIT(12), 0, BIT(12), RST_BASE_TYPE_APMU },
+	[RESET_CPU4_POP]    = { APMU_PMU_CC2_AP, BIT(16), 0, BIT(16), RST_BASE_TYPE_APMU },
+	[RESET_CPU4_SW]     = { APMU_PMU_CC2_AP, BIT(17), 0, BIT(17), RST_BASE_TYPE_APMU },
+	[RESET_CPU5_POP]    = { APMU_PMU_CC2_AP, BIT(19), 0, BIT(19), RST_BASE_TYPE_APMU },
+	[RESET_CPU5_SW]     = { APMU_PMU_CC2_AP, BIT(20), 0, BIT(20), RST_BASE_TYPE_APMU },
+	[RESET_CPU6_POP]    = { APMU_PMU_CC2_AP, BIT(22), 0, BIT(22), RST_BASE_TYPE_APMU },
+	[RESET_CPU6_SW]     = { APMU_PMU_CC2_AP, BIT(23), 0, BIT(23), RST_BASE_TYPE_APMU },
+	[RESET_CPU7_POP]    = { APMU_PMU_CC2_AP, BIT(25), 0, BIT(25), RST_BASE_TYPE_APMU },
+	[RESET_CPU7_SW]     = { APMU_PMU_CC2_AP, BIT(26), 0, BIT(26), RST_BASE_TYPE_APMU },
+	[RESET_C1_MPSUB_SW]      = { APMU_PMU_CC2_AP, BIT(28), 0, BIT(28), RST_BASE_TYPE_APMU },
+	[RESET_MPSUB_DBG]        = { APMU_PMU_CC2_AP, BIT(29), 0, BIT(29), RST_BASE_TYPE_APMU },
+	[RESET_UCIE]             = { APMU_UCIE_CTRL, BIT(1)|BIT(2)|BIT(3), BIT(1)|BIT(2)|BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_RCPU]             = { APMU_AUDIO_CLK_RES_CTRL, BIT(0)|BIT(2)|BIT(3), BIT(0)|BIT(2)|BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_DSI4LN2_ESCCLK]   = { APMU_LCD_CLK_RES_CTRL3, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_DSI4LN2_LCD_SW]   = { APMU_LCD_CLK_RES_CTRL3, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_DSI4LN2_LCD_MCLK]   = { APMU_LCD_CLK_RES_CTRL4, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU },
+	[RESET_DSI4LN2_LCD_DSCCLK] = { APMU_LCD_CLK_RES_CTRL4, BIT(15), BIT(15), 0, RST_BASE_TYPE_APMU },
+	[RESET_DSI4LN2_DPU_ACLK]   = { APMU_LCD_CLK_RES_CTRL5, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_DPU_ACLK]           = { APMU_LCD_CLK_RES_CTRL5, BIT(15), BIT(15), 0, RST_BASE_TYPE_APMU },
+	[RESET_UFS_ACLK]           = { APMU_UFS_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_EDP0]         = { APMU_LCD_EDP_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_EDP1]         = { APMU_LCD_EDP_CTRL, BIT(16), BIT(16), 0, RST_BASE_TYPE_APMU },
+	[RESET_PCIE_PORTA]   = { APMU_PCIE_CLK_RES_CTRL_PORTA, BIT(3)|BIT(4)|BIT(5), BIT(3)|BIT(4)|BIT(5), 0, RST_BASE_TYPE_APMU },
+	[RESET_PCIE_PORTB]   = { APMU_PCIE_CLK_RES_CTRL_PORTB, BIT(3)|BIT(4)|BIT(5), BIT(3)|BIT(4)|BIT(5), 0, RST_BASE_TYPE_APMU },
+	[RESET_PCIE_PORTC]   = { APMU_PCIE_CLK_RES_CTRL_PORTC, BIT(3)|BIT(4)|BIT(5), BIT(3)|BIT(4)|BIT(5), 0, RST_BASE_TYPE_APMU },
+	[RESET_PCIE_PORTD]   = { APMU_PCIE_CLK_RES_CTRL_PORTD, BIT(3)|BIT(4)|BIT(5), BIT(3)|BIT(4)|BIT(5), 0, RST_BASE_TYPE_APMU },
+	[RESET_PCIE_PORTE]   = { APMU_PCIE_CLK_RES_CTRL_PORTE, BIT(3)|BIT(4)|BIT(5), BIT(3)|BIT(4)|BIT(5), 0, RST_BASE_TYPE_APMU },
+	[RESET_EMAC0]        = { APMU_EMAC0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_EMAC1]        = { APMU_EMAC1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_EMAC2]        = { APMU_EMAC2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_ESPI]         = { APMU_ESPI_CLK_RES_CTRL, BIT(0)|BIT(2), BIT(0)|BIT(2), 0, RST_BASE_TYPE_APMU },
+	//DCIU
+	[RESET_HDMA]     = { DCIU_DMASYS_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_DMA350]   = { DCIU_DMASYS_SDMA_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_DMA350_0] = { DCIU_DMASYS_S0_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_DMA350_1] = { DCIU_DMASYS_S1_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_AXIDMA0]  = { DCIU_DMASYS_A0_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_AXIDMA1]  = { DCIU_DMASYS_A1_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_AXIDMA2]  = { DCIU_DMASYS_A2_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_AXIDMA3]  = { DCIU_DMASYS_A3_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_AXIDMA4]  = { DCIU_DMASYS_A4_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_AXIDMA5]  = { DCIU_DMASYS_A5_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_AXIDMA6]  = { DCIU_DMASYS_A6_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	[RESET_AXIDMA7]  = { DCIU_DMASYS_A7_RSTN, BIT(0), BIT(0), 0, RST_BASE_TYPE_DCIU },
+	//APBC2
+	[RESET_SEC_UART1]  = { APBC2_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_SSP2]   = { APBC2_SSP2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_TWSI3]  = { APBC2_TWSI3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_RTC]    = { APBC2_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_TIMERS] = { APBC2_TIMERS_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_JTAG]   = { APBC2_JTAG_SW_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_GPIO]   = { APBC2_GPIO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	//RCPU
+	//0xc088c000
+	[RESET_RCPU5_RT24_CORE0] = { RCPU5_RT24_CORE0_SW_RESET, BIT(0), 0, BIT(0), RST_BASE_TYPE_RCPU },
+	[RESET_RCPU5_RT24_CORE1] = { RCPU5_RT24_CORE1_SW_RESET, BIT(0), 0, BIT(0), RST_BASE_TYPE_RCPU },
+};
+
+static u32 spacemit_reset_read(struct spacemit_reset *reset, u32 id)
+{
+	void __iomem *base;
+
+	switch (reset->signals[id].type) {
+	case RST_BASE_TYPE_APMU:
+		base = reset->apmu_base;
+		break;
+	case RST_BASE_TYPE_APBC:
+		base = reset->apbc_base;
+		break;
+	case RST_BASE_TYPE_MPMU:
+		base = reset->mpmu_base;
+		break;
+	case RST_BASE_TYPE_APBS:
+		base = reset->apbs_base;
+		break;
+	case RST_BASE_TYPE_CIU:
+		base = reset->ciu_base;
+		break;
+	case RST_BASE_TYPE_DCIU:
+		base = reset->dciu_base;
+		break;
+	case RST_BASE_TYPE_DDRC:
+		base = reset->ddrc_base;
+		break;
+	case RST_BASE_TYPE_APBC2:
+		base = reset->apbc2_base;
+		break;
+	case RST_BASE_TYPE_RCPU:
+		base = reset->rcpu_base;
+		break;
+	default:
+		base = reset->apbc_base;
+		break;
+	}
+	return readl(base + reset->signals[id].offset);
+}
+
+static void spacemit_reset_write(struct spacemit_reset *reset, u32 value, u32 id)
+{
+	void __iomem *base;
+
+	switch (reset->signals[id].type) {
+	case RST_BASE_TYPE_APMU:
+		base = reset->apmu_base;
+		break;
+	case RST_BASE_TYPE_APBC:
+		base = reset->apbc_base;
+		break;
+	case RST_BASE_TYPE_MPMU:
+		base = reset->mpmu_base;
+		break;
+	case RST_BASE_TYPE_APBS:
+		base = reset->apbs_base;
+		break;
+	case RST_BASE_TYPE_CIU:
+		base = reset->ciu_base;
+		break;
+	case RST_BASE_TYPE_DCIU:
+		base = reset->dciu_base;
+		break;
+	case RST_BASE_TYPE_DDRC:
+		base = reset->ddrc_base;
+		break;
+	case RST_BASE_TYPE_APBC2:
+		base = reset->apbc2_base;
+		break;
+	case RST_BASE_TYPE_RCPU:
+		base = reset->rcpu_base;
+		break;
+	default:
+		base = reset->apbc_base;
+		break;
+	}
+
+	writel(value, base + reset->signals[id].offset);
+}
+
+static void spacemit_reset_set(struct reset_ctl *rst, u32 id, bool assert)
+{
+	u32 value;
+	struct spacemit_reset *reset = dev_get_priv(rst->dev);
+
+	value = spacemit_reset_read(reset, id);
+	if (assert == 1) {
+		value &= ~reset->signals[id].mask;
+		value |= reset->signals[id].assert_val;
+	} else {
+		value &= ~reset->signals[id].mask;
+		value |= reset->signals[id].deassert_val;
+	}
+
+	spacemit_reset_write(reset, value, id);
+}
+static int spacemit_reset_update(struct reset_ctl *rst, bool assert)
+{
+   	if (rst->id < RESET_UART0 || rst->id >= RESET_NUMBER)
+   		return 0;
+
+   	spacemit_reset_set(rst, rst->id, assert);
+   	return 0;
+}
+
+static int spacemit_reset_assert(struct reset_ctl *rst)
+{
+	return spacemit_reset_update(rst, true);
+}
+
+static int spacemit_reset_deassert(struct reset_ctl *rst)
+{
+	return spacemit_reset_update(rst, false);
+}
+
+static int spacemit_k3_reset_probe(struct udevice *dev)
+{
+	struct spacemit_reset *reset = dev_get_priv(dev);
+
+	reset->mpmu_base = (void __iomem *)dev_remap_addr_index(dev, 0);
+	if (!reset->mpmu_base) {
+		pr_err("failed to map mpmu registers\n");
+		goto out;
+	}
+
+	reset->apmu_base = (void __iomem *)dev_remap_addr_index(dev, 1);
+	if (!reset->apmu_base) {
+		pr_err("failed to map apmu registers\n");
+		goto out;
+	}
+
+	reset->apbc_base = (void __iomem *)dev_remap_addr_index(dev, 2);
+	if (!reset->apbc_base) {
+		pr_err("failed to map apbc registers\n");
+		goto out;
+	}
+
+	reset->apbs_base = (void __iomem *)dev_remap_addr_index(dev, 3);
+	if (!reset->apbs_base) {
+		pr_err("failed to map apbs registers\n");
+		goto out;
+	}
+
+	reset->ciu_base = (void __iomem *)dev_remap_addr_index(dev, 4);
+	if (!reset->ciu_base) {
+		pr_err("failed to map ciu registers\n");
+		goto out;
+	}
+
+	reset->dciu_base = (void __iomem *)dev_remap_addr_index(dev, 5);
+	if (!reset->dciu_base) {
+		pr_err("failed to map dragon ciu registers\n");
+		goto out;
+	}
+
+	reset->ddrc_base = (void __iomem *)dev_remap_addr_index(dev, 6);
+	if (!reset->ddrc_base) {
+		pr_err("failed to map ddrc registers\n");
+		goto out;
+	}
+
+	reset->apbc2_base = (void __iomem *)dev_remap_addr_index(dev, 7);
+	if (!reset->apbc2_base) {
+		pr_err("failed to map apbc2 registers\n");
+		goto out;
+	}
+
+	reset->rcpu_base = (void __iomem *)dev_remap_addr_index(dev, 8);
+	if (!reset->rcpu_base) {
+		pr_err("failed to map rcpu registers\n");
+		goto out;
+	}
+
+	reset->signals = k3_reset_signals;
+	pr_info("reset driver probe finish\n");
+
+out:
+  	return 0;
+}
+
+const struct reset_ops k3_reset_ops = {
+	.rst_assert = spacemit_reset_assert,
+	.rst_deassert = spacemit_reset_deassert,
+};
+
+static const struct udevice_id k3_reset_ids[] = {
+	{ .compatible = "spacemit,k3-reset", },
+	{},
+};
+
+U_BOOT_DRIVER(k3_reset) = {
+	.name		= "spacemit,k3-reset",
+	.id		= UCLASS_RESET,
+	.ops		= &k3_reset_ops,
+	.of_match	= k3_reset_ids,
+	.probe		= spacemit_k3_reset_probe,
+	.priv_auto	= sizeof(struct spacemit_reset),
+};
@@ -7,5 +7,8 @@
 #define __CONFIG_H

 #define CFG_SYS_NS16550_IER  0x40
-
+#define RISCV_SMODE_TIMER_FREQ  24000000
+#define RISCV_MMODE_TIMER_FREQ  24000000
+#define RISCV_MMODE_TIMERBASE   0xe081c000
+#define RISCV_MMODE_TIMEROFF    0xbff8
 #endif /* __CONFIG_H */
@@ -297,6 +297,7 @@
 #define OSC_32K                  290
 #define CLK_DUMMY                291

-#define CLK_MAX_NO               292
+#define CLK_TWSI2_BUS            292
+#define CLK_MAX_NO               293

 #endif /* _DT_BINDINGS_CLK_SPACEMIT_K3_H_ */
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR */
+/*
+ * Spacemit K3 reset controller driver
+ * Copyright (c) 2025, spacemit Corporation.
+ */
+
+#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K3_H__
+#define __DT_BINDINGS_RESET_SAPCEMIT_K3_H__
+//APBC
+#define RESET_UART0              0
+#define RESET_UART2              1
+#define RESET_UART3              2
+#define RESET_UART4              3
+#define RESET_UART5              4
+#define RESET_UART6              5
+#define RESET_UART7              6
+#define RESET_UART8              7
+#define RESET_UART9              8
+#define RESET_UART10             9
+#define RESET_GPIO               10
+#define RESET_PWM0               11
+#define RESET_PWM1               12
+#define RESET_PWM2               13
+#define RESET_PWM3               14
+#define RESET_PWM4               15
+#define RESET_PWM5               16
+#define RESET_PWM6               17
+#define RESET_PWM7               18
+#define RESET_PWM8               19
+#define RESET_PWM9               20
+#define RESET_PWM10              21
+#define RESET_PWM11              22
+#define RESET_PWM12              23
+#define RESET_PWM13              24
+#define RESET_PWM14              25
+#define RESET_PWM15              26
+#define RESET_PWM16              27
+#define RESET_PWM17              28
+#define RESET_PWM18              29
+#define RESET_PWM19              30
+#define RESET_SPI0               31
+#define RESET_SPI1               32
+#define RESET_SPI3               33
+#define RESET_RTC                34
+#define RESET_TWSI0              35
+#define RESET_TWSI1              36
+#define RESET_TWSI2              37
+#define RESET_TWSI4              38
+#define RESET_TWSI5              39
+#define RESET_TWSI6              40
+#define RESET_TWSI8              41
+#define RESET_TIMERS0            42
+#define RESET_TIMERS1            43
+#define RESET_TIMERS2            44
+#define RESET_TIMERS3            45
+#define RESET_TIMERS4            46
+#define RESET_TIMERS5            47
+#define RESET_TIMERS6            48
+#define RESET_TIMERS7            49
+#define RESET_AIB                50
+#define RESET_ONEWIRE            51
+#define RESET_I2S0               52
+#define RESET_I2S1               53
+#define RESET_I2S2               54
+#define RESET_I2S3               55
+#define RESET_I2S4               56
+#define RESET_I2S5               57
+#define RESET_DRO                58
+#define RESET_IR0                59
+#define RESET_IR1                60
+#define RESET_TSEN               61
+#define RESET_IPC_AP2AUD         62
+#define RESET_CAN0               63
+#define RESET_CAN1               64
+#define RESET_CAN2               65
+#define RESET_CAN3               66
+#define RESET_CAN4               67
+//MPMU
+#define RESET_WDT                68
+#define RESET_RIPC               69
+//APMU
+#define RESET_CSI                70
+#define RESET_CCIC2_PHY          71
+#define RESET_CCIC3_PHY          72
+#define RESET_ISP                73
+#define RESET_ISP_AHB            74
+#define RESET_ISP_CIBUS          75
+#define RESET_DSI_ESC            76
+#define RESET_LCD                77
+#define RESET_V2D                78
+#define RESET_LCD_SPI_HBUS       79
+#define RESET_LCD_SPI_BUS        80
+#define RESET_LCD_MCLK           81
+#define RESET_LCD_DSCCLK         82
+#define RESET_SC2_HCLK           83
+#define RESET_CCIC_4X            84
+#define RESET_CCIC1_PHY          85
+#define RESET_SDH_AXI            86
+#define RESET_SDH0               87
+#define RESET_SDH1               88
+#define RESET_SDH2               89
+#define RESET_USB2               90
+#define RESET_USB3_PORTA         91
+#define RESET_USB3_PORTB         92
+#define RESET_USB3_PORTC         93
+#define RESET_USB3_PORTD         94
+#define RESET_QSPI               95
+#define RESET_QSPI_BUS           96
+#define RESET_DMA                97
+#define RESET_AES_WTM            98
+#define RESET_MCB_DCLK           99
+#define RESET_MCB_ACLK           100
+#define RESET_VPU                101
+#define RESET_DTC                102
+#define RESET_GPU                103
+#define RESET_MC                 104
+#define RESET_CPU0_POP           105
+#define RESET_CPU0_SW            106
+#define RESET_CPU1_POP           107
+#define RESET_CPU1_SW            108
+#define RESET_CPU2_POP           109
+#define RESET_CPU2_SW            110
+#define RESET_CPU3_POP           111
+#define RESET_CPU3_SW            112
+#define RESET_C0_MPSUB_SW        113
+#define RESET_CPU4_POP           114
+#define RESET_CPU4_SW            115
+#define RESET_CPU5_POP           116
+#define RESET_CPU5_SW            117
+#define RESET_CPU6_POP           118
+#define RESET_CPU6_SW            119
+#define RESET_CPU7_POP           120
+#define RESET_CPU7_SW            121
+#define RESET_C1_MPSUB_SW        122
+#define RESET_MPSUB_DBG          123
+#define RESET_UCIE               124
+#define RESET_RCPU               125
+#define RESET_DSI4LN2_ESCCLK     126
+#define RESET_DSI4LN2_LCD_SW     127
+#define RESET_DSI4LN2_LCD_MCLK   128
+#define RESET_DSI4LN2_LCD_DSCCLK 129
+#define RESET_DSI4LN2_DPU_ACLK   130
+#define RESET_DPU_ACLK           131
+#define RESET_UFS_ACLK           132
+#define RESET_EDP0               133
+#define RESET_EDP1               134
+#define RESET_PCIE_PORTA         135
+#define RESET_PCIE_PORTB         136
+#define RESET_PCIE_PORTC         137
+#define RESET_PCIE_PORTD         138
+#define RESET_PCIE_PORTE         139
+#define RESET_EMAC0              140
+#define RESET_EMAC1              141
+#define RESET_EMAC2              142
+#define RESET_ESPI               143
+//DCIU
+#define RESET_HDMA               144
+#define RESET_DMA350             145
+#define RESET_DMA350_0           146
+#define RESET_DMA350_1           147
+#define RESET_AXIDMA0            148
+#define RESET_AXIDMA1            149
+#define RESET_AXIDMA2            150
+#define RESET_AXIDMA3            151
+#define RESET_AXIDMA4            152
+#define RESET_AXIDMA5            153
+#define RESET_AXIDMA6            154
+#define RESET_AXIDMA7            155
+//APBC2
+#define RESET_SEC_UART1          156
+#define RESET_SEC_SSP2           157
+#define RESET_SEC_TWSI3          158
+#define RESET_SEC_RTC            159
+#define RESET_SEC_TIMERS         160
+#define RESET_SEC_JTAG           161
+#define RESET_SEC_GPIO           162
+//RCPU
+#define RESET_RCPU5_RT24_CORE0   163
+#define RESET_RCPU5_RT24_CORE1   164
+
+#define RESET_NUMBER             165
+
+#endif /* __DT_BINDINGS_RESET_SAPCEMIT_K3_H__ */
Author	SHA1	Message	Date
ChuanN-sudo	c42f49ce2c	board: spacemit-k3: Add i2c driver	2026-05-30 15:28:19 +08:00
ChuanN-sudo	1c2e7d4f11	board: spacemit-k3: Add reset driver to support other deivers	2026-05-30 15:28:19 +08:00
ChuanN-sudo	e309628d73	board: spacemit-k3: Add early timer support for k3	2026-05-30 15:28:14 +08:00
ChuanN-sudo	547678ae3d	board: spacemit-k3:Update ccu driver to support i2c	2026-05-30 14:34:48 +08:00