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3 Commits

Author SHA1 Message Date
Ryder Lee
2d88b5a38e clk: MediaTek: add hifsys entry for MT7623 SoC. 
This adds high speed interface subsystem - hifsys (i.e. PCIe and USB)
for MT7623 SoC and enables its reset controller.

The control block is shared with ethsys and accordingly rename the
related defines.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
 2019-08-07 15:31:03 -04:00
Weijie Gao
2dca3cc2a9 clk: MediaTek: bind ethsys reset controller 
The ethsys contains not only the clock gating controller, but also the
reset controller for the whole ethernet subsystem and its components.

This patch adds binding of the reset controller so that the ethernet node
can have references on it.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 2019-01-14 17:43:18 -05:00
Ryder Lee
c746651550 clk: MediaTek: add clock driver for MT7623 SoC. 
This patch adds a driver for MT7623 clock blocks.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2018-11-28 23:04:51 -05:00