Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
(Please note that ISBC expects all these addresses, images to be
validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
at 0xcffffffc.
Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
(The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
created by PBL/configuration word within 0 - 3.5G memory range. The
u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
PBL/configuration word after switch to AS = 1
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: Wood Scott-B07421 <B07421@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.
SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
U-Boot BSP handle 0x3 offset for big endian systems.
Little endian Microblaze systems don't use any offset.
Signed-off-by: Michal Simek <monstr@monstr.eu>
The EST SBC8260 is over 10 years old, and the SBC8240 older than
that. With the tiny amount of RAM (by today's standards), there
really isn't anyone interested in running the latest U-boot on
these EOL products anymore.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: jon.diekema@smiths-aerospace.com
* 'post' of git://git.denx.de/u-boot-blackfin:
Blackfin: uart: implement loop callback for post
Blackfin: bf537-stamp/bf548-ezkit: update POST flash block range
Blackfin: post: generalize led/button tests with GPIOs
Blackfin: bf537-stamp: drop uart/flash post tests
Blackfin: post: drop custom test list
Blackfin: bf537-stamp: convert to gpio post hotkey
This magic constant with zero documentation, when it's last 8 bits are set to
0x45, configures correctly the PERCLK dividers. Therefore the I2C operates
correctly when divider computed from PERCLK.
Note: This constant is written to CBCDR register in
arch/arm/cpu/armv7/mx5/lowlevel_init.S, but it's written only once. The register
is accessed three more times in the file, with different values written to it
each time.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
The omap serial names have changed from ttySx to ttyOx,
so the console should be also changed to support this.
Signed-off-by: Thomas Weber <weber@corscience.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Change the default console from ttyS2 to ttyO0 to
match the Linux default for the EVM.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Config VMMC voltage to 3V for MMC/SD card slot
and PBIAS settings needed for OMAP4
Fixes MMC/SD detection on boot from eMMC.
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c.
The unified driver can initialize data using DDR controller. No need to
use DMA if just to initialze for ECC.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
USB protocol macros (CONFIG_USB_EHCI ...) to be included only when
CONFIG_HAS_FSL_DR_USB is defined for a board. Presence of USB DR controller
should be declared along with the underlying protocol used in the controller
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board.
The five dTSEC can be routed to two on-board RGMII phy, three on-board
SGMII phy or four SGMII phy on SGMII riser card according to different
serdes protocol configuration and board lane configuration. Also updated
the device tree to direct the Fmac MAC to the correct PHY.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P1023 has two 1G ethernet controllers the first can run in
SGMII, RGMII, or RMII. The second can only do SGMII & RGMII.
We need to setup a for SoC & board registers based on our various
configuration for ethernet to function properly on the board.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS.
The board supports add-on cards for SGMII and XAUI functionality. Which
slots on the board these cards are in is a function of the SERDES option
selected and muxes on the board.
Additionally because of the high-configurablity which MDIO bus one is
connected to is "selected" via an FPGA register. We create dummy MDIO
bus for the phy layer and hide the mux manipulation in this dummy layer.
Add fman fdt helper function in board common code it'll be used by several
freescale boards that do various muxing of the MDIO signals based on which
controller/interface one is trying to talk to.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.
P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
32Mbyte 16bit NOR flash
32Mbyte SLC NAND Flash
64KB CPLD device(GPCM interface)
SPI Flash:
128 Mbit SPI Flash memory
SD/MMC:
connector to interface with the SD memory card
SATA:
1 internal SATA connect to 2.5. 160G SATA2 HDD
1 eSATA connector to rear panel
USB 2.0:
x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
eTSEC1: Connected to RGMII PHY VSC8641XKO
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
Two DB-9 female connectors for Field bus interface
UART:
supports two UARTs up to 115200 bps for console
TDM:
2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
SPI SLIC
I2C:
Serial EEprom
Real time clock
256 Kbit M24256 I2C EEPROM
PCIe:
PCIe and mPCIe connectors.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The following boards share a common design but with minor variations
between them:
P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC
The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.
Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots
As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.
VSC firmware Address is defined by default in config file for eTSEC1.
SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.
Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b26998@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
This is necessary for the assembly-language code that relocates CCSR, since
the assembler does not understand 64-bit constants.
CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it
should not be defined in a board header file. Similarly,
CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
it should also not be defined in the board header file.
CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT,
and so CCSR will not be relocated.
Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
builds (e.g. NAND) are required to relocate CCSR only during the last stage
(i.e. the "real" U-Boot). All other stages should define
CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.
README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The few tests that are Blackfin-specific have been migrated to common
code or been rewritten with the existing "bsp-specific" defines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Factor out common parts from omap4_sdp4430.h and omap4_panda.h
into a new file omap4_common.h
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
