Surface RT is a hybrid tablet computer developed and manufactured
by Microsoft and shipped with Windows RT. The tablet uses a 1.3 GHz
quad-core Nvidia Tegra 3 chipset with 2 GB of RAM, features 10.8
inch 1366x768 screen and 32/64 GB of internal memory that can be
supplemented with a microSDXC card giving up to 200 GB of
additional storage.
Tested-by: Jethro Bull <jethrob@hotmail.com>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
WEXLER Tab 7t is a mini tablet computer developed by WEXLER that
runs the Android operating system. The device features a 7.0-inch
(180 mm) HD display, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM,
8, 16 or 32 GB of storage that can be supplemented with a microSDXC
card giving up to 64 GB of additional storage and a full size USB
port.
Tested-by: Maksim Kurnosenko <asusx2@mail.ru>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The Asus Eee Pad Transformer family are 2-in-1 detachable/slider
tablets developed by Asus that run the Android operating system.
The Eee Pad Transformers feature a 10.1-inch (260 mm) display,
an Nvidia Tegra 2 dual-core chip, 1 GB of RAM, and 16/32 GB of storage.
Transformers board derives from Nvidia Ventana development board.
This patch brings support for all 3 known T20 Transformers:
- Asus Eee Pad Transformer TF101
- Asus Eee Pad Transformer TF101G
- Asus Eee Pad Slider SL101
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101
Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # ASUS TF101
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Jiaxun Yang <jiaxun.yang@flygoat.com> says:
Hi all,
This series enabled qemu-xtensa board.
For dc232b CPU it needs to be built with toolchain[1].
This is a side product of me investigating architectures
physical address != virtual address in U-Boot. Now we can
get it covered under CI and regular tests.
VirtIO devices are not working as expected, due to U-Boot's
assumption on VA == PA everywhere, I'm going to get this fixed
later.
My Xtensa knowledge is pretty limited, Xtensa people please
feel free to point out if I got anything wrong.
Thanks
[1]: https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc232b-elf.tar.gz
This feature is not present on older Chromebooks, so disable the
setting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
We currently don't have any boards enabling CONFIG_EFI_RT_VOLATILE_STORE.
We do have EFI selftests testing the feature though, so enable it in
all the sandbox platforms and test the functionality properly
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Now that am335x_evm boots OK on the Beaglebone black, drop the latter
and update the docs to cover the change.
Also add a few updates about 'make fit' and drop the note about the
security review, as U-Boot's verified boot has had quite extensive
review now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This causes a hang, so disable it. Unfortunately the RAM-size fix does
not resolve the problem and I am unsure what is wrong. As soon as the
cache is enabled the board appears to hang.
Fixes: 6d8cdfd153 ("rockchip: spl: Enable caches to speed up checksum validation")
Signed-off-by: Simon Glass <sjg@chromium.org>
Set a size limit for this board so that we get a build error if it grows
too much.
Note that the limit is approximately, since it does not include the FDT,
microcode and fdtmap, which can change in size. However this board is
fairly stable, so overflowing this limit will likely result in the image
not fitting in the ROM space available for U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
This cannot be enabled early in boot since some other init is needed.
At this point it is unclear exactly what init is needed, so disable
the debug UART to avoid a hang.
Signed-off-by: Simon Glass <sjg@chromium.org>
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21310
- Enable SPL DTO application support for i.MX8MP DHCOM PDK2.
- Migrate imx8mn_bsh_smm_s2 and imx6ulz_bsh_smm_m2 to OF_UPSTREAM.
- Drop redundant imports with dts/upstream.
- Miscellaneous improvements for Gateworks i.MX8M boards.
Enable SPL DTO support to apply matching SoM specific DTOs to cater
for the SoM differences in DH i.MX8MP DHCOM PDK2 configuration. This
is already enabled in DH i.MX8MP DHCOM PDK3 configuration so align
the two configurations.
Fixes: ad1158c50e ("arm64: dts: imx8mp: Switch to DT overlays for i.MX8MP DHCOM SoM")
Signed-off-by: Marek Vasut <marex@denx.de>
It is good to be aware what information is shared via smbios interface
that's why enable it by default.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Enable ICSSG driver, DP83869 phy driver, REMOTEPROC and PRU_REMOTEPROC
in am64x_evm_a53_defconfig. All these configs are needed for ICSSG
driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Jayesh Choudhary <j-choudhary@ti.com> says:
Hello there,
This series add the U-Boot support for our new platform of K3-SOC
family - J722S-EVM which is a superset of AM62P. It shares the same
memory map and thus the nodes are being reused from AM62P includes
instead of duplicating the definitions.
Some highlights of J722S SoC (in addition to AM62P SoC features) are:
- Two Cortex-R5F for Functional Safety or general-purpose usage and
two C7x floating point vector DSP with Matrix Multiply Accelerator
for deep learning.
- Vision Processing Accelerator (VPAC) with image signal processor
and Depth and Motion Processing Accelerator (DMPAC).
- 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
ePWM, among other peripherals.
TRM: <https://www.ti.com/lit/zip/sprujb3>
Schematics: <https://www.ti.com/lit/zip/sprr495>
Boot test log:
<https://gist.github.com/Jayesh2000/0313e58fde377f877a9a8f1acc2579ef>
Introduce the initial configs needed to support the J722S SoC family.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
To better scale with the number of boards, separate TI K3 EFI capsule
configs into its own file that can be shared across TI K3 boards. This
will allow any platform level config changes to be done once.
Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com>
Enable mtd command and remove SPI NOR flashes we do not
populate on our SoMs.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Enable configs required for booting via DFU.
Configs taken from the am62x_a53_usbdfu.config config fragment.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Update environment location to align with OSPI fixed-partition
definitions and provide a redundant environment at a 2nd location.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Update environment location to align with OSPI fixed-partition
definitions and provide a redundant environment at a 2nd location.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Copy fixed-partitions nodes from U-Boot device tree to OS device tree.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
The default value CYCLIC_MAX_CPU_TIME_US was 1000, which is
a little bit too low for slower hardware and sandbox.
On my MIPS Boston FPGA board with interaptiv CPU, wdt_cyclic
can easily take 3200 us to run.
On azure pipeline sandbox_clang, wdt_cyclic some times goes
beyond 1300 us.
Raise default value to 5000, which is the value already taken
by octeon_nic32. This is still sufficent to maintain system
responsiveness.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
carrier board.
The SoM contains the following peripherals:
- STPMIC (power delivery)
- 512MB DDR3L memory
- eMMC and SDIO WiFi module
The DHSBC carrier board contains the following peripherals:
- Two RGMII Ethernet ports
- USB-A Host port, USB-C peripheral port, USB-C power supply plug
- Expansion connector
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
AMD/Xilinx changes for v2024.10-rc1
common:
- spl: Introduce SoC specific init function
xilinx:
- Enable FF-A and NVMEM
- Rename spl_board_init() to spl_soc_init()
zynqmp:
- DT alignments
- Enable reset from SPL
- Enable USB3 for KD240
- Align multiboot register on Kria for proper reboot
- Allow multiboot environment write even in saved environment
- Move zynqmp commands from board/ to arch/
- Clean up xilinx_zynqmp.h
versal:
- Do not prioritize boot device if driver is not enabled
versal-net:
- Setup location for redundant variables in SPI
versal2:
- Add support for new SOC
mmc:
- Fix tap delay for SD on Versal NET
spi:
- Add SPI_NOR_OCTAL_READ flag for mx66uw2g345gx0 flash part
gpio:
- Cover MODEPIN firmware dependency
