Commit Graph

4 Commits

Author SHA1 Message Date
Leo Yu-Chi Liang
dd3cd9eecc Revert "riscv: dts: jh7110: Enable PLL node in SPL"
This patch breaks speed SD function on Milk-V Mars CM Lite (DFRobot mini router carrier).
Revert this commit for now.

Link: https://lore.kernel.org/u-boot/ZpZSmdrst4z_Q4JQ@swlinux02/T/#mbcd32d430fe58a1dd8161c9f3cc073052501b701

This reverts commit e6b7aeef3d.

Reported-by: E Shattow <lucent@gmail.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-07-22 15:42:07 +08:00
Bo Gan
e6b7aeef3d riscv: dts: jh7110: Enable PLL node in SPL
Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12 14:36:13 +08:00
Xingyu Wu
6c4b50e6de riscv: dts: jh7110: Add clock source from PLL
Change the PLL clock source from syscrg to sys_syscon child node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24 13:21:06 +08:00
Yanhong Wang
c04dfc7ac1 riscv: dts: jh7110: Add initial u-boot device tree
Add initial u-boot device tree for the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20 20:45:07 +08:00