u-boot

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Author	SHA1	Message	Date
Chia-Wei Wang	3d99be97f1	aspeed: ast2600: Enlarge SRAM size The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>	2021-11-17 17:04:59 -05:00
Chia-Wei, Wang	4a84cf06aa	aspeed: Add AST2600 platform support Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>	2021-01-18 15:23:06 -05:00
Chia-Wei, Wang	98ef128b56	include/configs: aspeed: Remove hardcoded variables The hardcoded platform variables such as DRAM base address are not common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces those hardcoded with macros defined in a newly added header, where the basic SoC HW information are assigned accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>	2020-08-14 09:46:40 -04:00

Author

SHA1

Message

Date

Chia-Wei Wang

3d99be97f1

aspeed: ast2600: Enlarge SRAM size

The AST2600 SRAM has been extended to 88KB since A1
chip revision. This patch updates the SRAM size to
offer more space for early stack/heap use.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>

2021-11-17 17:04:59 -05:00

Chia-Wei, Wang

4a84cf06aa

aspeed: Add AST2600 platform support

Add low level platform initialization for the AST2600 SoC.
The 2-stage booting with U-Boot SPL are leveraged to support
different booting mode.

However, currently the patch supports only the booting from
memory-mapped SPI flash.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

2021-01-18 15:23:06 -05:00

Chia-Wei, Wang

98ef128b56

include/configs: aspeed: Remove hardcoded variables

The hardcoded platform variables such as DRAM base address are not
common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces
those hardcoded with macros defined in a newly added header, where
the basic SoC HW information are assigned accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>

2020-08-14 09:46:40 -04:00

3 Commits