3 Commits

Author	SHA1	Message	Date
Patrick Delaunay	bbd108a082	clk: stm32mp1: correctly handle Clock Spreading Generator ... To activate the csg option, the driver need to set the bit2 of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator of PLLn enable. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>	2019-02-09 07:50:57 -05:00
Patrick Delaunay	d219415544	stm32mp1: clk: support digital bypass ... HSE and LSE bypass shall support both analog and digital signals. This patch add a way to select digital bypas case in the device tree and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register during clock tree initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>	2018-07-20 15:55:07 -04:00
Patrick Delaunay	266fa4df00	clk: stm32mp1: add clock tree initialization ... add binding and code for clock tree initialization from device tree Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>	2018-03-19 16:14:22 -04:00