Commit Graph

4 Commits

Author SHA1 Message Date
Rui Miguel Silva
07ddbb89c9 clk: qcom: sm8650: add usb3 noc clk
Commit [0] introduced, correctly, the bubble of qcom clock errors to
make it easy to spot missing clocks in the platforms, and this is a case
of that, add the GCC_CFG_NOC_USB3_PRIM_AXI_CLK clock to sm8650 clock
pool.

0: 7c5460afec ("clk/qcom: bubble up qcom_gate_clk_en() errors")

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250618093253.225929-1-rui.silva@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14 15:35:24 +02:00
Caleb Connolly
7c5460afec clk/qcom: bubble up qcom_gate_clk_en() errors
If we try to enable a gate clock that doesn't exist, we used to just
fail silently. This may make sense for early bringup of some core
peripherals that we know are already enabled, but it only makes
debugging missing clocks more difficult.

Bubble up errors now that qcom_gate_clk_en() can return an error code to
catch any still-missing clocks and make it easier to find missing ones
as more complicated peripherals are enabled.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-03-17 15:12:15 +00:00
Neil Armstrong
bb77008c52 clk: qcom: sm8650: add support for PCIe clocks
Add the PCIe clocks for the SM8650 GCC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-3-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-22 16:36:16 +01:00
Neil Armstrong
c26fd49e90 clk: qcom: Add SM8650 clock driver
Add the GCC and TCSRCC clock driver for the SM8650 SoC.

The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.

The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.

The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23 13:29:11 +02:00