3 Commits

Author	SHA1	Message	Date
Yao Zi	5afad3d4a3	riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init ... C910 cores integrated in TH1520 SoC provide various customized CSRs for configuring core behavior, including cache coherency and timing, branch predication, and clock gating for internal components. This patch sets them up for efficient operation and satisfying requirements of an SMP system. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2025-07-03 16:14:13 +08:00
Yao Zi	ce8f49ece2	riscv: cpu: th1520: Initialize IOPMPs in SPL ... TH1520 SoC ships several IOPMPs protecting various on-chip peripherals. They must be configured before accessing the peripherals. Let's initialize them in SPL harts_early_init(). Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2025-05-21 16:49:57 +08:00
Yao Zi	5fe9ced355	riscv: cpu: Add TH1520 CPU support ... Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2025-05-21 16:49:52 +08:00