2 Commits

Author	SHA1	Message	Date
Yao Zi	85cfabe895	riscv: cpu: th1520: Support cache enabling/disabling in M mode only ... These operations rely on a customized M-mode CSR, MHCR, which isn't available when running in S mode. Let's fallback to the generic weak stub when running in S mode to avoid illegal accesses. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2025-06-09 10:44:06 +08:00
Yao Zi	5fe9ced355	riscv: cpu: Add TH1520 CPU support ... Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2025-05-21 16:49:52 +08:00