Commit Graph

28183 Commits

Author SHA1 Message Date
Anshul Dalal
2792cbf5d2 remoteproc: k3: update compatible for am654 syscon
The existing compatible name for U-Boot's k3 system controller driver
i.e "ti,am625-system-controller" has been added to linux[1] device-tree.
This compatible in kernel is meant for configuring the Control Module
registers (CTRL_MMR0).

However in U-Boot, the matching driver was being used to load the system
firmware on the secure M-cores by the R5 SPL and therefore must be
updated to a different compatible to avoid conflicts.

Therefore, this patch renames all references of the compatible to
"ti,am654-tisci-rproc-r5". The "-r5" is appended so as to avoid any
future conflicts since r5 specific compatibles should only be useful for
U-Boot.

[1]: 5959618631fe ("dt-bindings: mfd: ti,j721e-system-controller: Add compatible string for AM654")
     https://lore.kernel.org/r/20250421214620.3770172-2-afd@ti.com

Signed-off-by: Anshul Dalal <anshuld@ti.com>
2025-08-21 13:27:53 -06:00
Philip Molloy
55014ce40e mach-sc5xx: generate U-Boot proper in ADI ldr format
Generating an ldr boot stream containing U-Boot Proper was never added
to U-Boot because it is done by the ADI Yocto layer. Add it to U-Boot to
support projects that do not use that layer.

Signed-off-by: Philip Molloy <philip.molloy@analog.com>
2025-08-21 13:27:46 -06:00
Tom Rini
0572f7cad1 Merge patch series "Add support for Ethernet boot"
Chintan Vankar <c-vankar@ti.com> says:

This series adds bind method for CPSW to avoid explicit probing, removes
explicit probing of CPSW, adds support for Ethernet boot on SK-AM68,
SK-AM62P-LP, J722S, SK-AM69.

Link: https://lore.kernel.org/r/20250731075956.605474-1-c-vankar@ti.com
2025-08-20 11:37:59 -06:00
Chintan Vankar
721d5c30f5 arm: mach-k3: j784s4_spl: Alias Ethernet boot to CPGMAC
This is required to enable spl_net boot on SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
8eecd9edb5 arm: mach-k3: j784s4: Update SoC auto-gen data to enable Ethernet boot
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot for SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
a02009f3a8 arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Andreas Dannenberg
6fc2a6a971 arm: mach-k3: am62p: Update SoC auto-gen data to enable Ethernet boot
Update dev-data and clk-data to enable Ethernet boot using CPSW on
SK-AM62P-LP.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:19 -06:00
Chintan Vankar
e85b090165 arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC
This is required to enable spl_net boot on SK-AM68.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
0b092a2aa8 arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot
Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot.

Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
b4a0702c92 Revert "arm: mach-k3: am62x: am625_init: Probe AM65 CPSW NUSS"
This reverts commit 35bddf8896.

Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child
driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver
explicitly.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
3967d64740 Revert "mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL"
This reverts commit 93c43a8365.

Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child
driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver
explicitly.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Chintan Vankar
50ededad32 arch: mach-k3: common: Remove explicit probing of CPSW driver
This reverts commit e58d928485.

Bind method of am65_cpsw_nuss driver will ensure binding of it's child
driver am65_cpsw_nuss_ports, and there is no need to call CPSW driver
explicitly. Remove explicit probing of CPSW driver for AM62x.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
2025-08-20 11:06:18 -06:00
Tom Rini
66ff673a8e sandbox: Add generic asm/atomic.h
In order to compile code that uses <asm/atomic.h> on sandbox, we must
provide this header. RISC-V shows us today how to do so with the generic
header implementation, so copy that.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-19 11:25:28 -06:00
Tom Rini
58998fed9e sandbox: Improve dummy local_irq_save implementation
Normally, local_save_flags is used as part of the local_irq_* macros, so
remove that as it's unused. Make local_irq_save do something to the
passed variable so that it won't trigger unused variable warnings later.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-19 11:25:28 -06:00
Jim Liu
9878805816 misc: npcm_host_intf: Disable pending KCS/BPC interrupts
If there is an unhandled KCS/BPC pending interrupt after reboot,
the KCS/BPC Linux driver may trigger interrupts immediately upon
registering the irq. However, since the driver is not yet initialized
to handle them, this can lead to unexpected behavior.

To prevent this, disable KCS/BPC interrupts in u-boot to avoid pending
interrupts from being raised before the Linux driver is fully initialized.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:24 -06:00
Jim Liu
59a1c28755 arm: dts: nuvoton: Change timer node
npcm_timer driver is changed to use SECCNT counter.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:23 -06:00
Stanley Chu
6e212f32aa arm: dts: npcm8xx: add pinmux for VCD input
Add pinmux to select the HSYNC signal as the VCD input.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-08-18 16:40:23 -06:00
Tom Rini
d68db76b95 sandbox: Add an additional dummy sync macro
There are some drivers which call a "dmb" for a type of sync. Add that
as well to sandbox.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-14 10:58:43 -06:00
Quentin Schulz
28a87c8e9b rockchip: add /chosen/bootsource to U-Boot proper DT
U-Boot typically can be loaded from different storage media, such as
eMMC, SD card, SPI flash, but also from non-persistent media such as USB
(via proprietary protocols loading directly into SRAM, or fastboot, DFU,
 etc..), JTAG, ...

This information is usually reported by the BootROM via some proprietary
mechanism (some specific address in registers/DRAM for example). For
Rockchip, that information is stored in a register
(BROM_BOOTSOURCE_ID_ADDR).

While we already have the information about which medium was used to
load U-Boot proper from SPL (via /chosen/u-boot,spl-boot-device), this
new property represents the medium used to load U-Boot first phase
(depending on configuration, can be VPL/TPL/SPL) which absolutely may
differ from the one used to load U-Boot proper!

It would be useful to know which medium was used to load the first phase
of U-Boot, for example to check fallback mechanisms (proper loaded from
a different medium than first phase) are actually working.

For now, this only applies to Rockchip's U-Boot proper DT but could be
applied to the kernel's as well and possibly for other architectures or
vendors.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-08-13 12:42:05 -06:00
Shiji Yang
d78130ac5a arm: dts: mediatek: remove useless SPI property must_tx
This property is not documented. And the "mediatek,ipm-spi" SPI
driver doesn't check it.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
2025-08-11 15:11:22 -06:00
Tom Rini
493c3da3ac sandbox: Add more dummy functions to mimic other architectures
This adds more common functions found on other architectures that will
allow for more compile-testing of drivers. These are either dummy
functions as we do not need them or mappings to existing functions,
similar to how other architectures handle it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 15:11:19 -06:00
Tom Rini
26f857f1e3 arm: bcm235xx: Remove this SoC
As there are no platforms for this SoC, remove the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 15:00:33 -06:00
Tom Rini
92c54936fe Merge patch series "arch: arm: dts: k3-am625-phyboard-lyra: Disable unused watchdogs in U-Boot"
This series from Wadim Egorov <w.egorov@phytec.de> cleans up how
watchdogs are handled on some phytec TI K3 platforms.

Link: https://lore.kernel.org/r/20250730154217.1116751-1-w.egorov@phytec.de
2025-08-11 14:54:10 -06:00
Wadim Egorov
dcc85e9aba arch: arm: dts: k3-am642-phyboard-electra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Wadim Egorov
dfd185939d arch: arm: dts: k3-am62a7-phyboard-lyra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Wadim Egorov
b17c594ac4 arch: arm: dts: k3-am625-phyboard-lyra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Tom Rini
6d3382fad3 arm: socfpga: Correct how we set BOOTFILE
In order to set the BOOTFILE symbol we first need to have USE_BOOTFILE
be set, or some of the logic might not work as expected later on when
building. Second, defaults like this belong with the symbol itself.

Fixes: da595d236b ("include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile")
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-08-11 11:58:25 -06:00
Tom Rini
83ce0b483c Merge tag 'u-boot-socfpga-next-20250808' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.

Highlights:

- Agilex7 M-series bring-up:
  - Basic DT support and board initialization for Agilex7 M-series SoC and
    SoCDK.
  - New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
  - Clock driver support for Agilex7 M-series.
  - New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
  - Improved SPL support: ASYNC interrupt enabling, system manager init
    refactor, and cold scratch register usage.
  - Updated firewall probing and watchdog support in SPL.
  - Cleaned up DDR code, added secure region support for ATF, and improved warm
    reset handling.
- Device Tree and config updates:
  - Migration to upstream Linux DT layout for Agilex platforms.
  - Consolidated socfpga_agilex_defconfig and removed deprecated configs.
  - Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
  - dwc_eth_xgmac and clk-agilex cleanup and improvements.
  - Several coverity and style fixes.

Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody.  This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.

Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
2025-08-08 11:13:41 -06:00
Tom Rini
7ef148daa4 Merge tag 'u-boot-imx-master-20250808' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27314

- Several Smatch reported fixes.
- Enable the temperature command on imx8ulp-evk.
- Fix mx8mm_fracpll_tbl.
- Make optee packaging optional for imx8m.
- Reuse and export low_drive_freq_update() on imx9.
- Enable USB OTG ID pin pull up in SPL on dh-imx6.
2025-08-08 08:33:19 -06:00
Tingting Meng
2f429d2eb4 arch: arm: dts: Update Makefile for new platform Agilex7 M-series
Update Makefile to support Agilex7 M-series platform enablement.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:55 +08:00
Tingting Meng
605cf610c1 arch: arm: mach-socfpga: Update kconfig for new platform Agilex7 M-series
Update Kconfig for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:54 +08:00
Tingting Meng
0b5376b34a ddr: altera: Add DDR driver for Agilex7 M-series
This is for new platform enablement for Agilex7 M-series.
Add DDR driver for Agilex7 M-series. This driver is designed to support
DDR and HBM memory. The official HBM handoff is not ready yet, therefore
hardcoded handoff is used for HBM driver validation on mUDV board.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:54 +08:00
Tingting Meng
7a7c10054d clk: altera: Add clock support for Agilex7 M-series
Agilex7 M-series reuse the clock driver from Agilex.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:53 +08:00
Tingting Meng
da595d236b include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile
ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file
using bootm command.

Change to use CONFIG_SPL_ATF to differentiate the bootfile of default
environment variable. We shouldn't use CONFIG_FIT because it is enabled
by default for U-Boot Proper.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:53 +08:00
Tingting Meng
7ef12cd7b2 arch: arm: mach-socfpga: Update handoff settings for Agilex7 M-series
Handoff settings updated for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:52 +08:00
Tingting Meng
bd961f896f arch: arm: mach-socfpga: Improve help info.
To improve help info for bridge enable/disable command.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:52 +08:00
Tingting Meng
8f7d55037c arch: arm: mach-socfpga: Add Agilex7 M-series mach-socfgpa enablement
Add platform related files for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:51 +08:00
Tingting Meng
4f14fa7cff arch: arm: dts: Basic device tree support added for Agilex7 M-series
Agilex7 M-series support has been added using upstream Linux DTS.

socfpga_agilex_socdk-u-boot.dtsi was updated to support both Agilex and
Agilex7 M-series platforms.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:51 +08:00
Tingting Meng
78c44977a2 arch: arm: dts: agilex: Switch to using upstream Linux DT config
Migrate the legacy Agilex platform to use the upstream Linux device tree
configuration. This helps reduce maintenance overhead and aligns U-Boot
with the Linux kernel's DTS hierarchy and naming conventions.

This change improves consistency between U-Boot and Linux by removing
custom/legacy DTS handling and instead relying on the standardized
definitions provided by the upstream Linux DTS.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:51 +08:00
Tingting Meng
c465ff14a3 arch: arm: agilex: Clean up DT settings in U-Boot dtsi files
Reorganize misplaced properties by moving board-common settings from
socfpga_agilex_socdk-u-boot.dtsi to socfpga_agilex-u-boot.dtsi to maintain
proper separation between common and board-level configurations.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:50 +08:00
Alif Zakuan Yuslaimi
71916a72f1 arm: socfpga: soc64: Perform warm reset after L2 reset in SPL
SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system register and also enters WFI mode.

This warm reset flow is handled entirely within the HPS. The
function `socfpga_sysreset_request()` triggers the warm
reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S`
handles the necessary initialization.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:50 +08:00
Alif Zakuan Yuslaimi
c8f5166cff sysreset: socfpga: soc64: Enable L2 reset
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:50 +08:00
Alif Zakuan Yuslaimi
3a1cd4ffd7 arm: socfpga: misc: Exclude Agilex from clock manager base address retrieval
Agilex retrieves its clock manager address via probing its own clock
driver model during the SPL initialization.

Therefore, excluding Agilex from calling its clock driver in misc
driver to retrieve the clock manager address.

Once all SoC64 devices has been successfully transition to clock
driver model method, this implementation will be cleaned up.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:49 +08:00
Alif Zakuan Yuslaimi
1e354de7fc ddr: altera: agilex: Get ACF from boot scratch register
The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.

By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured accurately.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:49 +08:00
Alif Zakuan Yuslaimi
209d53eb1b arm: socfpga: Define the usage of boot scratch cold reg 8
The boot scratch cold reg 8 is shared between DBE, DDR init progress
update and Linux EDAC. This patch defines how the bits are used by
respective features above and their macro names used in U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:48 +08:00
Alif Zakuan Yuslaimi
1dc683005d arm: socfpga: agilex: Enable system manager driver for Agilex
The base address of system manager can be retrieved
using DT framework through the system manager driver.

Enable system manager support for Agilex by probing the
system manager driver to initialize during SPL boot up.

Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:48 +08:00
Alif Zakuan Yuslaimi
5416a3a306 arm: socfpga: agilex5: Refactor system manager driver initialization
Refactor system manager initialization by searching for system manager
alias in Agilex5 device tree instead of manually passing node name to
the device model calling function

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:47 +08:00
Alif Zakuan Yuslaimi
6a4453ab06 drivers: watchdog: Enable watchdog support in SPL for Agilex
Enable watchdog as early as possible after clock initialization
which is set at 10 seconds.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:20:46 +08:00
Tien Fong Chee
3721998510 arm: socfpga: Enable ASYNC interrupts in Agilex SPL
Asynchronous aborts were previously masked at SPL
entry.

To ensure early detection of system errors
such as ECC faults or bus errors, asynchronous aborts
should be explicitly unmasked by clearing the A-bit in
the DAIF register during Agilex SPL initialization.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

# Conflicts:
#	arch/arm/mach-socfpga/spl_agilex.c
2025-08-08 22:20:42 +08:00
Alif Zakuan Yuslaimi
677147c167 arm: socfpga: Update Agilex SPL data save and restore implementation
Enable backup for data section to support warm reset in Agilex SPL as
no SPL image would be reloaded in warm reset.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-08-08 22:19:23 +08:00