Fix bug for npcm7xx bmc calculate pll clock. PLLCON1 need to divide by 2. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
Add clock controller driver for NPCM750 Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>