forked from OERV-BSP/u-boot
Merge tag 'net-20250818' of https://source.denx.de/u-boot/custodians/u-boot-net
Pull request net-20250818. This is mostly code cleanup and fixes, mainly for issues reported by the Smatch tool, plus two small features for NET_LWIP as well as support for the BCM54612E phy. net-common: - Fix a bunch of issues reported by Smatch - Introduce CONFIG_DNS - Add support for BCM54612E phy net-legacy: - Add missing SPDX-License-Identifier for files originating from LiMon net-lwip: - ping: initialize net_try_count to 1 - sntp: remove redundant sys_check_timeouts() - tftp: resend initial request - Add Kconfig option to show ICMP unreachable errors
This commit is contained in:
@@ -499,7 +499,7 @@ static int ca_phy_probe(struct udevice *dev)
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dev, priv->phy_interface);
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if (ext_phydev) {
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ext_phydev->supported &= PHY_GBIT_FEATURES;
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ext_phydev->advertising = int_phydev->supported;
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ext_phydev->advertising = ext_phydev->supported;
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phy_config(ext_phydev);
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} else {
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printf("CA NI %s: There is no external phy device\n", __func__);
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@@ -486,7 +486,7 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
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#ifdef CONFIG_ARCH_NPCM8XX
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
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unsigned int start;
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ulong start;
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/* Indirect access to VR_MII_MMD registers */
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writew((VR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
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@@ -532,7 +532,7 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
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{
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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unsigned int start;
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ulong start;
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int ret;
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writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
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@@ -347,11 +347,6 @@ static int ks8851_mll_detect_chip(struct ks_net *ks)
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debug("Read back KS8851 id 0x%x\n", val);
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if ((val & 0xfff0) != CIDER_ID) {
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printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
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return -1;
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}
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return 0;
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}
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@@ -458,7 +458,7 @@ static int ldpaa_eth_open(struct udevice *dev)
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link_state.up == 1 ? printf("up\n") : printf("error state\n");
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#endif
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memset(&d_queue, 0, sizeof(struct dpni_queue));
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memset(&d_queue, 0, sizeof(struct dpni_queue_id));
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err = dpni_get_queue(dflt_mc_io, MC_CMD_NO_FLAGS,
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dflt_dpni->dpni_handle, DPNI_QUEUE_RX,
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0, 0, &d_queue_cfg, &d_queue);
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@@ -1461,7 +1461,7 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
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priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
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if (priv->phy_addr < 0) {
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printf("error: phy address is not specified\n");
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return ret;
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return priv->phy_addr;
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}
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}
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@@ -631,7 +631,7 @@ static int mv88e6xxx_port_enable(struct udevice *dev, int port, struct phy_devic
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dev_dbg(dev, "configure internal RGMII delays\n");
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/* RGMII delays */
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val &= ~(PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK ||
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val &= ~(PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK |
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PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK);
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if (phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phy->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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@@ -1722,8 +1722,7 @@ static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
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}
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/* Return first free tcam index, seeking from start to end */
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static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
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unsigned char end)
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static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, int start, int end)
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{
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int tid;
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@@ -2330,7 +2329,7 @@ static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
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pe = kzalloc(sizeof(*pe), GFP_KERNEL);
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if (!pe)
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return -1;
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return -ENOMEM;
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mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
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pe->index = tid;
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@@ -4735,7 +4734,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
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int port_node = dev_of_offset(dev);
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int phy_node;
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u32 id;
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u32 phyaddr = 0;
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int phyaddr = 0;
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int fixed_link = 0;
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int ret;
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@@ -5354,7 +5353,7 @@ static int mvpp2_probe(struct udevice *dev)
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} else {
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port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"gop-port-id", -1);
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if (port->id == -1) {
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if (port->gop_id == -1) {
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dev_err(dev, "missing gop-port-id value\n");
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return -EINVAL;
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}
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@@ -232,7 +232,7 @@ static int nicvf_rcv_pkt_handler(struct nicvf *nic,
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size_t pkt_len;
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struct cqe_rx_t *cqe_rx = (struct cqe_rx_t *)cq_desc;
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int err = 0;
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int err;
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/* Check for errors */
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err = nicvf_check_cqe_rx_errs(nic, cq, cq_desc);
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@@ -245,8 +245,7 @@ static int nicvf_rcv_pkt_handler(struct nicvf *nic,
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return -1;
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}
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if (pkt)
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*ppkt = pkt;
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*ppkt = pkt;
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return pkt_len;
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}
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@@ -274,31 +273,29 @@ int nicvf_cq_handler(struct nicvf *nic, void **ppkt, int *pkt_len)
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cqe_head >>= 9;
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cqe_head &= 0xFFFF;
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if (cqe_count) {
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/* Get the CQ descriptor */
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cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
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cqe_head++;
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cqe_head &= (cq->dmem.q_len - 1);
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/* Get the CQ descriptor */
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cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
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cqe_head++;
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cqe_head &= (cq->dmem.q_len - 1);
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switch (cq_desc->cqe_type) {
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case CQE_TYPE_RX:
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debug("%s: Got Rx CQE\n", nic->dev->name);
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*pkt_len = nicvf_rcv_pkt_handler(nic, cq, cq_desc,
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ppkt, CQE_TYPE_RX);
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processed_rq_cqe++;
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break;
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case CQE_TYPE_SEND:
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debug("%s: Got Tx CQE\n", nic->dev->name);
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nicvf_snd_pkt_handler(nic, cq, cq_desc, CQE_TYPE_SEND);
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processed_sq_cqe++;
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break;
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default:
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debug("%s: Got CQ type %u\n", nic->dev->name,
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cq_desc->cqe_type);
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break;
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}
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processed_cqe++;
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switch (cq_desc->cqe_type) {
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case CQE_TYPE_RX:
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debug("%s: Got Rx CQE\n", nic->dev->name);
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*pkt_len = nicvf_rcv_pkt_handler(nic, cq, cq_desc,
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ppkt, CQE_TYPE_RX);
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processed_rq_cqe++;
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break;
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case CQE_TYPE_SEND:
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debug("%s: Got Tx CQE\n", nic->dev->name);
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nicvf_snd_pkt_handler(nic, cq, cq_desc, CQE_TYPE_SEND);
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processed_sq_cqe++;
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break;
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default:
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debug("%s: Got CQ type %u\n", nic->dev->name,
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cq_desc->cqe_type);
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break;
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}
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processed_cqe++;
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/* Dequeue CQE */
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nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
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@@ -338,7 +338,8 @@ int octeontx_smi_probe(struct udevice *dev)
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if (!bus || !priv) {
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printf("Failed to allocate OcteonTX MDIO bus # %u\n",
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dev_seq(dev));
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return -1;
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ret = -ENOMEM;
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goto error_ret;
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}
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bus->read = octeontx_phy_read;
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@@ -355,9 +356,16 @@ int octeontx_smi_probe(struct udevice *dev)
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ret = mdio_register(bus);
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if (ret)
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return ret;
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goto error_ret;
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}
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return 0;
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error_ret:
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if (bus)
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free(bus);
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if (priv)
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free(priv);
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return ret;
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}
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static const struct udevice_id octeontx_smi_ids[] = {
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@@ -298,6 +298,8 @@ int nix_lf_setup(struct nix *nix)
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goto error;
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}
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err = -1;
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/* Alloc memory for Qints HW contexts */
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nix->qint_base = nix_memalloc(nix_af->qints, nix_af->qint_ctx_sz,
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"Qint CTX");
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@@ -114,7 +114,7 @@ struct nix_af *rvu_af_init(struct rvu_af *rvu_af)
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return nix_af;
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error:
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if (nix_af->npa_af) {
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if (nix_af && nix_af->npa_af) {
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free(nix_af->npa_af);
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memset(nix_af, 0, sizeof(*nix_af));
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}
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@@ -134,6 +134,33 @@ static void bcm_phy_write_misc(struct phy_device *phydev,
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value);
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}
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/* Broadcom BCM54612E */
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static int bcm54612e_config(struct phy_device *phydev)
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{
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u32 reg = 0;
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genphy_config_aneg(phydev);
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phy_reset(phydev);
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/* 125Mhz Clock Output Enable */
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL);
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reg |= 0xD34;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
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reg |= (1 << 1);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, reg);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL);
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reg &= 0xfffff000;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg);
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genphy_restart_aneg(phydev);
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return 0;
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}
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/* Broadcom BCM5461S */
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static int bcm5461_config(struct phy_device *phydev)
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{
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@@ -434,6 +461,16 @@ U_BOOT_PHY_DRIVER(bcm5461s) = {
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.shutdown = &genphy_shutdown,
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};
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U_BOOT_PHY_DRIVER(bcm54612e) = {
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.name = "Broadcom BCM54612E",
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.uid = 0x03625e6a,
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.mask = 0xfffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &bcm54612e_config,
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.startup = &bcm54xx_startup,
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.shutdown = &genphy_shutdown,
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};
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U_BOOT_PHY_DRIVER(bcm5464s) = {
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.name = "Broadcom BCM5464S",
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.uid = 0x2060b0,
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@@ -239,7 +239,7 @@ static int vsc8514_config(struct phy_device *phydev)
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while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--)
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
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if (0 == timeout) {
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if (timeout == -1) {
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printf("PHY 8514 config failed\n");
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return -1;
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}
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@@ -225,11 +225,6 @@ static const struct reg_field pllctrl_lock =
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static const struct reg_field phy_iso_link_ctrl_1 =
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REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
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static const char * const clk_names[] = {
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[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
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[CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
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};
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enum cdns_sierra_cmn_plllc {
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CMN_PLLLC,
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CMN_PLLLC1,
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@@ -602,7 +597,7 @@ static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
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struct udevice *dev = sp->dev;
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struct driver *cdns_sierra_clk_drv;
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struct cdns_sierra_pll_mux_sel *data = pll_clk_mux_sel;
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int i, rc;
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int rc;
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cdns_sierra_clk_drv = lists_driver_lookup_name("cdns_sierra_mux_clk");
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if (!cdns_sierra_clk_drv) {
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@@ -612,10 +607,8 @@ static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
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rc = device_bind(dev, cdns_sierra_clk_drv, "pll_mux_clk",
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data, dev_ofnode(dev), NULL);
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if (rc) {
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dev_err(dev, "cannot bind driver for clock %s\n",
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clk_names[i]);
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}
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if (rc)
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dev_err(dev, "cannot bind driver for clock pll_mux_clk\n");
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return 0;
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}
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@@ -719,6 +719,7 @@ static int cdns_torrent_phy_probe(struct udevice *dev)
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if (total_num_lanes > MAX_NUM_LANES) {
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dev_err(dev, "Invalid lane configuration\n");
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ret = -EINVAL;
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goto put_lnk_rst;
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}
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@@ -28,7 +28,7 @@ static const char *get_speed_string(u32 speed)
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"10.3125 Gbps"
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};
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if (speed < 0 || speed > COMPHY_SPEED_MAX)
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if (speed < 0 || speed >= COMPHY_SPEED_MAX)
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return "invalid";
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return speed_strings[speed];
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@@ -44,7 +44,7 @@ static const char *get_type_string(u32 type)
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"IGNORE"
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};
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if (type < 0 || type > COMPHY_TYPE_MAX)
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if (type < 0 || type >= COMPHY_TYPE_MAX)
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return "invalid";
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return type_strings[type];
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@@ -47,8 +47,8 @@ struct chip_serdes_phy_config {
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int (*rx_training)(struct chip_serdes_phy_config *, u32);
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void __iomem *comphy_base_addr;
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void __iomem *hpipe3_base_addr;
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u32 comphy_lanes_count;
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u32 comphy_mux_bitcount;
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int comphy_lanes_count;
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int comphy_mux_bitcount;
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const fdt32_t *comphy_mux_lane_order;
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u32 cp_index;
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struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
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Block a user