forked from OERV-BSP/u-boot
doc: remove redundant Rockchip bindings
Most Rockchip device tree related bindings are converted to YAML and available in the U-boot /dts/upstream/Bindings/ directory. Remove all redundant U-boot entries. Signed-off-by: Johan Jonker <jbx6244@gmail.com>
This commit is contained in:
Johan Jonker
committed by
Heinrich Schuchardt
Heinrich Schuchardt
parent
a7dc9f3220
commit
4888d1bd0e
@@ -1,61 +0,0 @@
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* Rockchip RK3188/RK3066 Clock and Reset Unit
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The RK3188/RK3066 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
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"rockchip,rk3066a-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing pll rates are not changable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
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dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
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Similar macros exist for the reset sources in these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "xin32k" - rtc clock - optional,
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- "xin27m" - 27mhz crystal input on rk3066 - optional,
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- "ext_hsadc" - external HSADC clock - optional,
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- "ext_cif0" - external camera clock - optional,
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- "ext_rmii" - external RMII clock - optional,
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- "ext_jtag" - externalJTAG clock - optional
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Example: Clock controller node:
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cru: cru@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@10124000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10124000 0x400>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cru SCLK_UART0>;
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};
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@@ -1,61 +0,0 @@
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* Rockchip RK3288 Clock and Reset Unit
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The RK3288 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: should be "rockchip,rk3288-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing pll rates are not changable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "xin32k" - rtc clock - optional,
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- "ext_i2s" - external I2S clock - optional,
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- "ext_hsadc" - external HSADC clock - optional,
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- "ext_edp_24m" - external display port clock - optional,
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- "ext_vip" - external VIP clock - optional,
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- "ext_isp" - external ISP clock - optional,
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- "ext_jtag" - external JTAG clock - optional
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Example: Clock controller node:
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cru: cru@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@10124000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10124000 0x400>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cru SCLK_UART0>;
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};
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@@ -1,77 +0,0 @@
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Device Tree Clock bindings for arch-rockchip
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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== Gate clocks ==
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These bindings are deprecated!
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Please use the soc specific CRU bindings instead.
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The gate registers form a continuos block which makes the dt node
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structure a matter of taste, as either all gates can be put into
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one gate clock spanning all registers or they can be divided into
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the 10 individual gates containing 16 clocks each.
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The code supports both approaches.
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Required properties:
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- compatible : "rockchip,rk2928-gate-clk"
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- reg : shall be the control register address(es) for the clock.
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- #clock-cells : from common clock binding; shall be set to 1
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- clock-output-names : the corresponding gate names that the clock controls
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- clocks : should contain the parent clock for each individual gate,
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therefore the number of clocks elements should match the number of
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clock-output-names
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Example using multiple gate clocks:
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clk_gates0: gate-clk@200000d0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d0 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_core_periph", "gate_cpu_gpll",
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"gate_ddrphy", "gate_aclk_cpu",
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"gate_hclk_cpu", "gate_pclk_cpu",
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"gate_atclk_cpu", "gate_i2s0",
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"gate_i2s0_frac", "gate_i2s1",
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"gate_i2s1_frac", "gate_i2s2",
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"gate_i2s2_frac", "gate_spdif",
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"gate_spdif_frac", "gate_testclk";
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#clock-cells = <1>;
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};
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clk_gates1: gate-clk@200000d4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d4 0x4>;
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clocks = <&xin24m>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&dummy>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>;
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clock-output-names =
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"gate_timer0", "gate_timer1",
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"gate_timer2", "gate_jtag",
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"gate_aclk_lcdc1_src", "gate_otgphy0",
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"gate_otgphy1", "gate_ddr_gpll",
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"gate_uart0", "gate_frac_uart0",
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"gate_uart1", "gate_frac_uart1",
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"gate_uart2", "gate_frac_uart2",
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"gate_uart3", "gate_frac_uart3";
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#clock-cells = <1>;
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};
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