arm: renesas: Use stock lowlevel_init function and remove s_init

Replace s_init() early initialization at the end of lowlevel_init
by invoking the same code in mach_cpu_init(). The mach_cpu_init()
is called a bit later, but as the code initializes timer and no
code uses timer until mach_cpu_init(), this does not pose a problem.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

arch/arm/mach-renesas/lowlevel_init_gen3.S

@@ -30,74 +30,3 @@ ENTRY(save_boot_params)
 	stp	x2, x3, [x8], #16
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
-
-.pushsection .text.s_init, "ax"
-WEAK(s_init)
-	ret
-ENDPROC(s_init)
-.popsection
-
-ENTRY(lowlevel_init)
-	mov	x29, lr			/* Save LR */
-
-#ifndef CONFIG_ARMV8_MULTIENTRY
-	/*
-	 * For single-entry systems the lowlevel init is very simple.
-	 */
-	ldr	x0, =GICD_BASE
-	bl	gic_init_secure
-
-#else /* CONFIG_ARMV8_MULTIENTRY is set */
-
-#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-	branch_if_slave x0, 1f
-	ldr	x0, =GICD_BASE
-	bl	gic_init_secure
-1:
-#if defined(CONFIG_GICV3)
-	ldr	x0, =GICR_BASE
-	bl	gic_init_secure_percpu
-#elif defined(CONFIG_GICV2)
-	ldr	x0, =GICD_BASE
-	ldr	x1, =GICC_BASE
-	bl	gic_init_secure_percpu
-#endif
-#endif
-
-	branch_if_master x0, 2f
-
-	/*
-	 * Slave should wait for master clearing spin table.
-	 * This sync prevent salves observing incorrect
-	 * value of spin table and jumping to wrong place.
-	 */
-#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-#ifdef CONFIG_GICV2
-	ldr	x0, =GICC_BASE
-#endif
-	bl	gic_wait_for_interrupt
-#endif
-
-	/*
-	 * All slaves will enter EL2 and optionally EL1.
-	 */
-	adr	x4, lowlevel_in_el2
-	ldr	x5, =ES_TO_AARCH64
-	bl	armv8_switch_to_el2
-
-lowlevel_in_el2:
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
-	adr	x4, lowlevel_in_el1
-	ldr	x5, =ES_TO_AARCH64
-	bl	armv8_switch_to_el1
-
-lowlevel_in_el1:
-#endif
-#endif /* CONFIG_ARMV8_MULTIENTRY */
-
-	bl      s_init
-
-2:
-	mov	lr, x29			/* Restore LR */
-	ret
-ENDPROC(lowlevel_init)

board/renesas/common/gen3-spl.c

@@ -29,10 +29,6 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_UART;
 }
 
-void s_init(void)
-{
-}
-
 void reset_cpu(void)
 {
 }

board/renesas/common/gen4-common.c

@@ -41,10 +41,12 @@ static void init_gic_v3(void)
 	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
 }
 
-void s_init(void)
+int mach_cpu_init(void)
 {
 	if (current_el() == 3)
 		init_generic_timer();
+
+	return 0;
 }
 
 int board_early_init_f(void)

board/renesas/common/gen4-spl.c

@@ -82,7 +82,7 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
 #define RTGRP3_BIT			BIT(19)
 #define APMU_ACC_ENB_FOR_ARM_CPU	(CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
 
-void s_init(void)
+int mach_cpu_init(void)
 {
 	/* Unlock CPG access */
 	writel(0x5A5AFFFF, CPGWPR);
@@ -95,6 +95,8 @@ void s_init(void)
 	writel(0x00ff00ff, APMU_BASE + 0x18);
 	writel(0x00ff00ff, APMU_BASE + 0x1c);
 	clrbits_le32(APMU_BASE + 0x68, BIT(29));
+
+	return 0;
 }
 
 void reset_cpu(void)

board/renesas/common/gen5-common.c

@@ -37,10 +37,12 @@ static void init_gic_v3(void)
 	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
 }
 
-void s_init(void)
+int mach_cpu_init(void)
 {
 	if (current_el() == 3)
 		init_generic_timer();
+
+	return 0;
 }
 
 int board_early_init_f(void)