// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 NXP
 */

#include <dt-bindings/clock/imx8ulp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8ulp-power.h>

#include "imx8ulp-pinfunc.h"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec;
		gpio0 = &gpiod;
		gpio1 = &gpioe;
		gpio2 = &gpiof;
		mmc0 = &usdhc0;
		mmc1 = &usdhc1;
		mmc2 = &usdhc2;
		serial0 = &lpuart4;
		serial1 = &lpuart5;
		serial2 = &lpuart6;
		serial3 = &lpuart7;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		A35_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
		};

		A35_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
		};

		A35_L2: l2-cache0 {
			compatible = "cache";
		};
	};

	gic: interrupt-controller@2d400000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu {
		compatible = "arm,cortex-a35-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7
			     (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-affinity = <&A35_0>, <&A35_1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
	};

	frosc: clock-frosc {
		compatible = "fixed-clock";
		clock-frequency = <192000000>;
		clock-output-names = "frosc";
		#clock-cells = <0>;
	};

	lposc: clock-lposc {
		compatible = "fixed-clock";
		clock-frequency = <1000000>;
		clock-output-names = "lposc";
		#clock-cells = <0>;
	};

	rosc: clock-rosc {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "rosc";
		#clock-cells = <0>;
	};

	sosc: clock-sosc {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "sosc";
		#clock-cells = <0>;
	};

	sram@2201f000 {
		compatible = "mmio-sram";
		reg = <0x0 0x2201f000 0x0 0x1000>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x2201f000 0x1000>;

		scmi_buf: scmi-sram-section@0 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0x400>;
		};
	};

	firmware {
		scmi {
			compatible = "arm,scmi-smc";
			arm,smc-id = <0xc20000fe>;
			#address-cells = <1>;
			#size-cells = <0>;
			shmem = <&scmi_buf>;

			scmi_devpd: protocol@11 {
				reg = <0x11>;
				#power-domain-cells = <1>;
			};

			scmi_sensor: protocol@15 {
				reg = <0x15>;
				#thermal-sensor-cells = <1>;
			};
		};
	};

	soc: soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x40000000>;

		s4muap: mailbox@27020000 {
			compatible = "fsl,imx8ulp-mu-s4";
			reg = <0x27020000 0x10000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <2>;
		};

		per_bridge3: bus@29000000 {
			compatible = "simple-bus";
			reg = <0x29000000 0x800000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			mu: mailbox@29220000 {
				compatible = "fsl,imx8ulp-mu";
				reg = <0x29220000 0x10000>;
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				#mbox-cells = <2>;
				status = "disabled";
			};

			mu3: mailbox@29230000 {
				compatible = "fsl,imx8ulp-mu";
				reg = <0x29230000 0x10000>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
				#mbox-cells = <2>;
				status = "disabled";
			};

			wdog3: watchdog@292a0000 {
				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
				reg = <0x292a0000 0x10000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
				timeout-sec = <40>;
			};

			cgc1: clock-controller@292c0000 {
				compatible = "fsl,imx8ulp-cgc1";
				reg = <0x292c0000 0x10000>;
				#clock-cells = <1>;
			};

			pcc3: clock-controller@292d0000 {
				compatible = "fsl,imx8ulp-pcc3";
				reg = <0x292d0000 0x10000>;
				#clock-cells = <1>;
				#reset-cells = <1>;
			};

			tpm5: tpm@29340000 {
				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
				reg = <0x29340000 0x1000>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
					 <&pcc3 IMX8ULP_CLK_TPM5>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			lpi2c4: i2c@29370000 {
				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x29370000 0x10000>;
				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
				clock-names = "per", "ipg";
				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
				assigned-clock-rates = <48000000>;
				status = "disabled";
			};

			lpi2c5: i2c@29380000 {
				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x29380000 0x10000>;
				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
				clock-names = "per", "ipg";
				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
				assigned-clock-rates = <48000000>;
				status = "disabled";
			};

			lpuart4: serial@29390000 {
				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x29390000 0x1000>;
				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpuart5: serial@293a0000 {
				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x293a0000 0x1000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpspi4: spi@293b0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
				reg = <0x293b0000 0x10000>;
				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
				clock-names = "per", "ipg";
				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
				assigned-clock-rates = <48000000>;
				status = "disabled";
			};

			lpspi5: spi@293c0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
				reg = <0x293c0000 0x10000>;
				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
				clock-names = "per", "ipg";
				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
				assigned-clock-rates = <48000000>;
				status = "disabled";
			};
		};

		per_bridge4: bus@29800000 {
			compatible = "simple-bus";
			reg = <0x29800000 0x800000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pcc4: clock-controller@29800000 {
				compatible = "fsl,imx8ulp-pcc4";
				reg = <0x29800000 0x10000>;
				#clock-cells = <1>;
				#reset-cells = <1>;
			};

			lpi2c6: i2c@29840000 {
				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x29840000 0x10000>;
				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
				clock-names = "per", "ipg";
				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
				assigned-clock-rates = <48000000>;
				status = "disabled";
			};

			lpi2c7: i2c@29850000 {
				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x29850000 0x10000>;
				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
				clock-names = "per", "ipg";
				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
				assigned-clock-rates = <48000000>;
				status = "disabled";
			};

			lpuart6: serial@29860000 {
				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x29860000 0x1000>;
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpuart7: serial@29870000 {
				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x29870000 0x1000>;
				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
				clock-names = "ipg";
				status = "disabled";
			};

			iomuxc1: pinctrl@298c0000 {
				compatible = "fsl,imx8ulp-iomuxc1";
				reg = <0x298c0000 0x10000>;
			};

			usdhc0: mmc@298d0000 {
				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
				reg = <0x298d0000 0x10000>;
				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
					 <&pcc4 IMX8ULP_CLK_USDHC0>;
				clock-names = "ipg", "ahb", "per";
				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc1: mmc@298e0000 {
				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
				reg = <0x298e0000 0x10000>;
				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
					 <&pcc4 IMX8ULP_CLK_USDHC1>;
				clock-names = "ipg", "ahb", "per";
				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@298f0000 {
				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
				reg = <0x298f0000 0x10000>;
				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
					 <&pcc4 IMX8ULP_CLK_USDHC2>;
				clock-names = "ipg", "ahb", "per";
				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			fec: ethernet@29950000 {
				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
				reg = <0x29950000 0x10000>;
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "int0";
				fsl,num-tx-queues = <1>;
				fsl,num-rx-queues = <1>;
				status = "disabled";
			};
		};

		gpioe: gpio@2d000080 {
				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
					 <&pcc4 IMX8ULP_CLK_PCTLE>;
				clock-names = "gpio", "port";
				gpio-ranges = <&iomuxc1 0 32 24>;
		};

		gpiof: gpio@2d010080 {
				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
					 <&pcc4 IMX8ULP_CLK_PCTLF>;
				clock-names = "gpio", "port";
				gpio-ranges = <&iomuxc1 0 64 32>;
		};

		per_bridge5: bus@2d800000 {
			compatible = "simple-bus";
			reg = <0x2d800000 0x800000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			cgc2: clock-controller@2da60000 {
				compatible = "fsl,imx8ulp-cgc2";
				reg = <0x2da60000 0x10000>;
				#clock-cells = <1>;
			};

			pcc5: clock-controller@2da70000 {
				compatible = "fsl,imx8ulp-pcc5";
				reg = <0x2da70000 0x10000>;
				#clock-cells = <1>;
				#reset-cells = <1>;
			};
		};

		gpiod: gpio@2e200080 {
			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
				 <&pcc5 IMX8ULP_CLK_RGPIOD>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 0 24>;
		};
	};
};
