// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
 * Author: Matt McKee <mmckee@phytec.com>
 *
 * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
 * Author: Wadim Egorov <w.egorov@phytec.de>
 */

/dts-v1/;

#include "k3-am642-phyboard-electra-rdk.dts"
#include "k3-am64-phycore-som-ddr4-2gb.dtsi"
#include "k3-am64-ddr.dtsi"

#include "k3-am642-phyboard-electra-rdk-u-boot.dtsi"

/ {
	aliases {
		ethernet0 = &cpsw3g;
		remoteproc0 = &sysctrler;
		remoteproc1 = &a53_0;
	};

	a53_0: a53@0 {
		compatible = "ti,am654-rproc";
		reg = <0x00 0x00a90000 0x00 0x10>;
		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
		resets = <&k3_reset 135 0>;
		clocks = <&k3_clks 61 0>;
		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
		assigned-clock-parents = <&k3_clks 61 2>;
		assigned-clock-rates = <200000000>, <1000000000>;
		ti,sci = <&dmsc>;
		ti,sci-proc-id = <32>;
		ti,sci-host-id = <10>;
		bootph-pre-ram;
	};

	clk_200mhz: dummy-clock-200mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <200000000>;
		bootph-pre-ram;
	};

	vtt_supply: vtt-supply {
		compatible = "regulator-fixed";
		regulator-name = "vtt";
		pinctrl-names = "default";
		pinctrl-0 = <&ddr_vtt_pins_default>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&main_gpio0 14 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
		regulator-boot-on;
		bootph-pre-ram;
	};
};

&cbass_main {
	sysctrler: sysctrler {
		compatible = "ti,am654-tisci-rproc-r5";
		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
		mbox-names = "tx", "rx";
		bootph-pre-ram;
	};
};

&cbass_mcu {
	bootph-pre-ram;
};

&dmsc {
	mboxes= <&secure_proxy_main 0>,
		<&secure_proxy_main 1>,
		<&secure_proxy_main 0>;
	mbox-names = "rx", "tx", "notify";
	ti,host-id = <35>;
	ti,secure-host;
};

&main_esm {
	bootph-pre-ram;
};

&main_gpio0 {
	bootph-pre-ram;
};

&main_pmx0 {
	bootph-pre-ram;
	ddr_vtt_pins_default: ddr-vtt-default-pins {
		bootph-pre-ram;
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0038, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN3.GPIO0_14 */
		>;
	};
};

/* timer init is called as part of rproc_start() while
 * starting System Firmware, so any clock/power-domain
 * operations will fail as SYSFW is not yet up and running.
 * Delete all clock/power-domain properties to avoid
 * timer init failure.
 * This is an always on timer at 20MHz.
 */
&main_timer0 {
	/delete-property/ clocks;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	/delete-property/ power-domains;
};

/* UART is initialized before SYSFW is started
 * so we can't do any power-domain/clock operations.
 * Delete clock/power-domain properties to avoid
 * UART init failure
 */
&main_uart0 {
	/delete-property/ power-domains;
	/delete-property/ clocks;
	/delete-property/ clock-names;
};

&mcu_esm {
	bootph-pre-ram;
};

&memorycontroller {
	vtt-supply = <&vtt_supply>;
};

&ospi0 {
	reg = <0x00 0x0fc40000 0x00 0x100>,
	      <0x00 0x60000000 0x00 0x08000000>;
};
