if ARCH_SOCFPGA

config ERR_PTR_OFFSET
	default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range

config NR_DRAM_BANKS
	default 1

config SOCFPGA_SECURE_VAB_AUTH
	bool "Enable boot image authentication with Secure Device Manager"
	depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \
	  TARGET_SOCFPGA_AGILEX5
	select FIT_IMAGE_POST_PROCESS
	select SHA384
	select SHA512
	select SPL_FIT_IMAGE_POST_PROCESS
	help
	 All images loaded from FIT will be authenticated by Secure Device
	 Manager.

config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
	bool "Allow non-FIT VAB signed images"
	depends on SOCFPGA_SECURE_VAB_AUTH

config SPL_SIZE_LIMIT
	default 0x10000 if TARGET_SOCFPGA_GEN5

config SPL_SIZE_LIMIT_PROVIDE_STACK
	default 0x200 if TARGET_SOCFPGA_GEN5

config SPL_STACK_R_ADDR
	default 0x00800000 if TARGET_SOCFPGA_GEN5

config SPL_SYS_MALLOC_F
	default y if TARGET_SOCFPGA_GEN5

config SPL_SYS_MALLOC_F_LEN
	default 0x800 if TARGET_SOCFPGA_GEN5

config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
	default 0xa2

config SYS_MALLOC_F_LEN
	default 0x2000 if TARGET_SOCFPGA_ARRIA10
	default 0x2000 if TARGET_SOCFPGA_GEN5

config TEXT_BASE
	default 0x01000040 if TARGET_SOCFPGA_ARRIA10
	default 0x01000040 if TARGET_SOCFPGA_GEN5

config TARGET_SOCFPGA_AGILEX
	bool
	select ARMV8_MULTIENTRY
	select ARMV8_SET_SMPEN
	select BINMAN if SPL_ATF
	select CLK
	select FPGA_INTEL_SDM_MAILBOX
	select GICV2
	select NCORE_CACHE
	select SPL_CLK if SPL
	select TARGET_SOCFPGA_SOC64

config TARGET_SOCFPGA_AGILEX7M
	bool
	select ARMV8_MULTIENTRY
	select ARMV8_SET_SMPEN
	select BINMAN if SPL_ATF
	select CLK
	select FPGA_INTEL_SDM_MAILBOX
	select GICV2
	select NCORE_CACHE
	select SPL_CLK if SPL
	select TARGET_SOCFPGA_SOC64

config TARGET_SOCFPGA_AGILEX5
	bool
	select BINMAN if SPL_ATF
	select CLK
	select FPGA_INTEL_SDM_MAILBOX
	select SPL_CLK if SPL
	select TARGET_SOCFPGA_SOC64

config TARGET_SOCFPGA_ARRIA5
	bool
	select TARGET_SOCFPGA_GEN5

config TARGET_SOCFPGA_ARRIA10
	bool
	select GICV2
	select SPL_ALTERA_SDRAM
	select SPL_BOARD_INIT if SPL
	select SPL_CACHE if SPL
	select CLK
	select SPL_CLK if SPL
	select DM_I2C
	select DM_RESET
	select SPL_DM_RESET if SPL
	select REGMAP
	select SPL_REGMAP if SPL
	select SYSCON
	select SPL_SYSCON if SPL
	select ETH_DESIGNWARE_SOCFPGA
	imply FPGA_SOCFPGA
	imply SPL_USE_TINY_PRINTF

config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
	bool "Always reprogram Arria 10 FPGA"
	depends on TARGET_SOCFPGA_ARRIA10
	help
	  Arria 10 FPGA is only programmed during the cold boot.
	  This option forces the FPGA to be reprogrammed every reboot,
	  allowing to change the bitstream and apply it with warm reboot.

config TARGET_SOCFPGA_CYCLONE5
	bool
	select TARGET_SOCFPGA_GEN5

config TARGET_SOCFPGA_GEN5
	bool
	select SPL_ALTERA_SDRAM
	imply FPGA_SOCFPGA
	imply SPL_SIZE_LIMIT_SUBTRACT_GD
	imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
	imply SPL_STACK_R
	imply SPL_SYS_MALLOC_SIMPLE
	imply SPL_USE_TINY_PRINTF

config TARGET_SOCFPGA_N5X
	bool
	select ARMV8_MULTIENTRY
	select ARMV8_SET_SMPEN
	select BINMAN if SPL_ATF
	select CLK
	select GICV2
	select NCORE_CACHE
	select SPL_ALTERA_SDRAM
	select SPL_CLK if SPL
	select TARGET_SOCFPGA_SOC64

config TARGET_SOCFPGA_N5X_SOCDK
	bool "Intel eASIC SoCDK (N5X)"
	select TARGET_SOCFPGA_N5X

config TARGET_SOCFPGA_SOC64
	bool

config TARGET_SOCFPGA_STRATIX10
	bool
	select ARMV8_MULTIENTRY
	select ARMV8_SET_SMPEN
	select BINMAN if SPL_ATF
	select FPGA_INTEL_SDM_MAILBOX
	select GICV2
	select TARGET_SOCFPGA_SOC64

choice
	prompt "Altera SOCFPGA board select"
	optional

config TARGET_SOCFPGA_AGILEX_SOCDK
	bool "Intel SOCFPGA SoCDK (Agilex)"
	select TARGET_SOCFPGA_AGILEX

config TARGET_SOCFPGA_AGILEX7M_SOCDK
	bool "Intel SOCFPGA SoCDK (Agilex7 M-series)"
	select TARGET_SOCFPGA_AGILEX7M

config TARGET_SOCFPGA_AGILEX5_SOCDK
	bool "Intel SOCFPGA SoCDK (Agilex5)"
	select TARGET_SOCFPGA_AGILEX5

config TARGET_SOCFPGA_ARIES_MCVEVK
	bool "Aries MCVEVK (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_ARRIA10_SOCDK
	bool "Altera SOCFPGA SoCDK (Arria 10)"
	select TARGET_SOCFPGA_ARRIA10

config TARGET_SOCFPGA_ARRIA5_SECU1
	bool "ABB SECU1 (Arria V)"
	select TARGET_SOCFPGA_ARRIA5
	select VENDOR_KM

config TARGET_SOCFPGA_ARRIA5_SOCDK
	bool "Altera SOCFPGA SoCDK (Arria V)"
	select TARGET_SOCFPGA_ARRIA5

config TARGET_SOCFPGA_CHAMELEONV3
	bool "Google Chameleon v3 (Arria 10)"
	select TARGET_SOCFPGA_ARRIA10

config TARGET_SOCFPGA_CYCLONE5_SOCDK
	bool "Altera SOCFPGA SoCDK (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
	bool "Devboards DBM-SoC1 (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_EBV_SOCRATES
	bool "EBV SoCrates (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_IS1
	bool "IS1 (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_SOFTING_VINING_FPGA
	bool "Softing VIN|ING FPGA (Cyclone V)"
	select BOARD_LATE_INIT
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_SR1500
	bool "SR1500 (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_STRATIX10_SOCDK
	bool "Intel SOCFPGA SoCDK (Stratix 10)"
	select TARGET_SOCFPGA_STRATIX10

config TARGET_SOCFPGA_TERASIC_DE0_NANO
	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_TERASIC_DE10_NANO
	bool "Terasic DE10-Nano (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
	bool "Terasic DE10-Standard (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_TERASIC_DE1_SOC
	bool "Terasic DE1-SoC (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

config TARGET_SOCFPGA_TERASIC_SOCKIT
	bool "Terasic SoCkit (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

endchoice

config SYS_BOARD
	default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK
	default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
	default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
	default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
	default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
	default "is1" if TARGET_SOCFPGA_IS1
	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
	default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
	default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
	default "sr1500" if TARGET_SOCFPGA_SR1500
	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
	default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA

config SYS_VENDOR
	default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK
	default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK
	default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
	default "intel" if TARGET_SOCFPGA_N5X_SOCDK
	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
	default "google" if TARGET_SOCFPGA_CHAMELEONV3
	default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
	default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT

config SYS_SOC
	default "socfpga"

config SYS_CONFIG_NAME
	default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK
	default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
	default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
	default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
	default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
	default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
	default "socfpga_is1" if TARGET_SOCFPGA_IS1
	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
	default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA

endif
