// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
 * Christoph Stoidner <c.stoidner@phytec.de>
 * Copyright (C) 2024 PHYTEC Messtechnik GmbH
 *
 * Product homepage:
   https://www.phytec.de/produkte/system-on-modules/phycore-imx-91-93/
 */

#include "imx93-u-boot.dtsi"

/ {
	/*
	 * The phyCORE-i.MX93 u-boot uses the imx93-phyboard-segin.dts as
	 * reference, but does only make use of its SoM (phyCORE) contained
	 * periphery.
	 */
	model = "PHYTEC phyCORE-i.MX93";

	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&wdog3>;
		bootph-pre-ram;
		bootph-some-ram;
	};

	aliases {
		ethernet0 = &fec;
		ethernet1 = &eqos;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

&{/soc@0} {
	bootph-all;
	bootph-pre-ram;
};

&aips1 {
	bootph-pre-ram;
	bootph-all;
};

&aips2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&aips3 {
	bootph-pre-ram;
	bootph-some-ram;
};

&iomuxc {
	bootph-pre-ram;
	bootph-some-ram;
};

&reg_usdhc2_vmmc {
	u-boot,off-on-delay-us = <20000>;
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_lpi2c3 {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_pmic {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_reg_usdhc2_vmmc {
	bootph-pre-ram;
};

&pinctrl_uart1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc1_100mhz {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc1_200mhz {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc2_cd {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc2_default {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc2_100mhz {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc2_200mhz {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio3 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio4 {
	bootph-pre-ram;
	bootph-some-ram;
};

&lpuart1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&usdhc1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&usdhc2 {
	bootph-pre-ram;
	bootph-some-ram;
	fsl,signal-voltage-switch-extra-delay-ms = <8>;
};

&lpi2c1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&lpi2c2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&lpi2c3 {
	bootph-pre-ram;
	bootph-some-ram;

	pmic@25 {
		bootph-pre-ram;
		bootph-some-ram;

		regulators {
			bootph-pre-ram;
			bootph-some-ram;
		};
	};

	eeprom@50 {
		bootph-pre-ram;
		bootph-some-ram;
	};
};

&s4muap {
	bootph-pre-ram;
	bootph-some-ram;
	status = "okay";
};

&clk {
	bootph-all;
	bootph-pre-ram;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-rates;
	/delete-property/ assigned-clock-parents;
};

&osc_32k {
	bootph-all;
	bootph-pre-ram;
};

&osc_24m {
	bootph-all;
	bootph-pre-ram;
};

&clk_ext1 {
	bootph-all;
	bootph-pre-ram;
};

&wdog3 {
	bootph-all;
	bootph-pre-ram;
};
