// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) 2022
 * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
 * Giulio Benetti <giulio.benetti@benettiengineering.com>
 */

#include "armv7-m.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1170-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/memory/imxrt-sdram.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
		gpio7 = &gpio8;
		gpio8 = &gpio9;
		gpio9 = &gpio10;
		gpio10 = &gpio11;
		gpio11 = &gpio12;
		gpio12 = &gpio13;
		mmc0 = &usdhc1;
		serial0 = &lpuart1;
	};

	clocks {
		osc: osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};

		rcosc16M: rcosc16M {
			compatible = "fsl,imx-osc", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <16000000>;
		};

		osc32k: osc32k {
			compatible = "fsl,imx-osc", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

	};

	soc {
		semc: semc@400d4000 {
			compatible = "fsl,imxrt-semc";
			reg = <0x400d4000 0x4000>;
			interrupts = <132>;
			clocks = <&clks IMXRT1170_CLK_SEMC>;
			pinctrl-0 = <&pinctrl_semc>;
			pinctrl-names = "default";
			status = "okay";
		};

		lpuart1: serial@4007c000 {
			compatible = "fsl,imxrt-lpuart";
			reg = <0x4007c000 0x4000>;
			interrupts = <20>;
			clocks = <&clks IMXRT1170_CLK_LPUART1>;
			clock-names = "per";
			status = "disabled";
		};

		iomuxc: iomuxc@400e8000 {
			compatible = "fsl,imxrt-iomuxc";
			reg = <0x400e8000 0x4000>;
		};

		anatop: anatop@40c84000 {
			compatible = "fsl,imxrt-anatop";
			reg = <0x40c84000 0x4000>;
		};

		clks: ccm@40cc0000 {
			compatible = "fsl,imxrt1170-ccm";
			reg = <0x40cc0000 0x4000>;
			#clock-cells = <1>;
		};

		usdhc1: usdhc@40418000 {
			compatible = "fsl,imxrt-usdhc";
			reg = <0x40418000 0x10000>;
			interrupts = <133>;
			clocks = <&clks IMXRT1170_CLK_USDHC1>;
			clock-names = "per";
			bus-width = <4>;
			fsl,tuning-start-tap = <20>;
			fsl,tuning-step= <2>;
			status = "disabled";
		};

		gpio1: gpio@4012c000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x4012c000 0x4000>;
			interrupts = <100>,
				     <101>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@40130000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40130000 0x4000>;
			interrupts = <102>,
				<103>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@40134000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40134000 0x4000>;
			interrupts = <104>,
				<105>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@40138000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40138000 0x4000>;
			interrupts = <106>,
					<107>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@4013c000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x4013c000 0x4000>;
			interrupts = <108>,
				<109>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@40140000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40140000 0x4000>;
			interrupts = <61>,
				<62>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio7: gpio@40c5c000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40c5c000 0x4000>;
			interrupts = <99>,
				<99>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio8: gpio@40c60000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40c60000 0x4000>;
			interrupts = <99>,
				<99>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio9: gpio@40c64000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40c64000 0x4000>;
			interrupts = <99>,
				<99>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio10: gpio@40c68000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40c68000 0x4000>;
			interrupts = <99>,
				<99>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio11: gpio@40c6c000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40c6c000 0x4000>;
			interrupts = <99>,
				<99>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio12: gpio@40c70000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40c70000 0x4000>;
			interrupts = <61>,
				<62>; // only cm4
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio13: gpio@40ca0000 {
			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
			reg = <0x40ca0000 0x4000>;
			interrupts = <93>,
				<93>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		flexspi1: spi@400cc000 {
			compatible = "nxp,imxrt1170-fspi";
			reg = <0x400cc000 0x800>, <0x30000000 0x10000000>;
			reg-names = "fspi_base", "fspi_mmap";
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <130>;
			clocks = <&clks IMXRT1170_CLK_DUMMY>,
				<&clks IMXRT1170_CLK_FLEXSPI1>;
			clock-names = "fspi_en", "fspi";
			status = "disabled";
		};

		gpt1: gpt1@400ec000 {
			compatible = "fsl,imxrt-gpt";
			reg = <0x400ec000 0x4000>;
			interrupts = <119>;
			clocks = <&clks IMXRT1170_CLK_GPT1>;
			status = "disabled";
		};
	};
};
