/*
 * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
 * Ethernet interface.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 *
 * Licensed under GPLv2.
 */

#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	ahb {
		apb {
			pmc: pmc@fffffc00 {
				periphck {
					can0_clk: can0_clk@29 {
						#clock-cells = <0>;
						reg = <29>;
					};

					can1_clk: can1_clk@30 {
						#clock-cells = <0>;
						reg = <30>;
					};
				};
			};

			can0: can@f8000000 {
				compatible = "atmel,at91sam9x5-can";
				reg = <0xf8000000 0x300>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_can0_rx_tx>;
				clocks = <&can0_clk>;
				clock-names = "can_clk";
				status = "disabled";
			};

			can1: can@f8004000 {
				compatible = "atmel,at91sam9x5-can";
				reg = <0xf8004000 0x300>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_can1_rx_tx>;
				clocks = <&can1_clk>;
				clock-names = "can_clk";
				status = "disabled";
			};

			pinctrl@fffff400 {
				can0 {
					pinctrl_can0_rx_tx: can0_rx_tx {
						atmel,pins =
							<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0, conflicts with DRXD */
							AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* CANTX0, conflicts with DTXD */
					};
				};

				can1 {
					pinctrl_can1_rx_tx: can1_rx_tx {
						atmel,pins =
							<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1, conflicts with RXD1 */
							AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* CANTX1, conflicts with TXD1 */
					};
				};
			};
		};
	};
};
