// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx93.dtsi"

/ {
	compatible = "fsl,imx93-11x11-frdm", "fsl,imx93";
	model = "NXP i.MX93 11X11 FRDM board";

	aliases {
		mmc0 = &usdhc1; /* EMMC */
		mmc1 = &usdhc2; /* uSD */
		rtc0 = &pcf2131;
		serial0 = &lpuart1;
	};

	chosen {
		stdout-path = &lpuart1;
	};

	reg_vref_1v8: regulator-adc-vref {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-name = "vref_1v8";
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		off-on-delay-us = <12000>;
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		pinctrl-names = "default";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "VSD_3V3";
		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc3_vmmc: regulator-usdhc3 {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "WLAN_EN";
		gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		/*
		 * IW612 wifi chip needs more delay than other wifi chips to complete
		 * the host interface initialization after power up, otherwise the
		 * internal state of IW612 may be unstable, resulting in the failure of
		 * the SDIO3.0 switch voltage.
		 */
		startup-delay-us = <20000>;
	};

	reserved-memory {
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x80000000 0 0x30000000>;
			reusable;
			size = <0 0x10000000>;
			linux,cma-default;
		};

		rsc_table: rsc-table@2021e000 {
			reg = <0 0x2021e000 0 0x1000>;
			no-map;
		};

		vdev0vring0: vdev0vring0@a4000000 {
			reg = <0 0xa4000000 0 0x8000>;
			no-map;
		};

		vdev0vring1: vdev0vring1@a4008000 {
			reg = <0 0xa4008000 0 0x8000>;
			no-map;
		};

		vdev1vring0: vdev1vring0@a4010000 {
			reg = <0 0xa4010000 0 0x8000>;
			no-map;
		};

		vdev1vring1: vdev1vring1@a4018000 {
			reg = <0 0xa4018000 0 0x8000>;
			no-map;
		};

		vdevbuffer: vdevbuffer@a4020000 {
			compatible = "shared-dma-pool";
			reg = <0 0xa4020000 0 0x100000>;
			no-map;
		};
	};

	usdhc3_pwrseq: usdhc3_pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
	};
};

&adc1 {
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&eqos {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii-id";
	pinctrl-0 = <&pinctrl_eqos>;
	pinctrl-1 = <&pinctrl_eqos_sleep>;
	pinctrl-names = "default", "sleep";
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
			reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
		};
	};
};

&fec {
	phy-handle = <&ethphy2>;
	phy-mode = "rgmii-id";
	pinctrl-0 = <&pinctrl_fec>;
	pinctrl-1 = <&pinctrl_fec_sleep>;
	pinctrl-names = "default", "sleep";
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy2: ethernet-phy@2 {
			reg = <2>;
			eee-broken-1000t;
			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
			reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
		};
	};
};

&lpi2c2 {
	clock-frequency = <400000>;
	pinctrl-0 = <&pinctrl_lpi2c2>;
	pinctrl-names = "default";
	status = "okay";

	pcal6524: gpio@22 {
		compatible = "nxp,pcal6524";
		reg = <0x22>;
		#interrupt-cells = <2>;
		interrupt-controller;
		interrupt-parent = <&gpio3>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
		#gpio-cells = <2>;
		gpio-controller;
		pinctrl-0 = <&pinctrl_pcal6524>;
		pinctrl-names = "default";
	};

	pmic@25 {
		compatible = "nxp,pca9451a";
		reg = <0x25>;
		interrupt-parent = <&pcal6524>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;

		regulators {

			buck1: BUCK1 {
				regulator-name = "BUCK1";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <650000>;
				regulator-max-microvolt = <2237500>;
				regulator-ramp-delay = <3125>;
			};

			buck2: BUCK2 {
				regulator-name = "BUCK2";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-ramp-delay = <3125>;
			};

			buck4: BUCK4 {
				regulator-name = "BUCK4";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
			};

			buck5: BUCK5 {
				regulator-name = "BUCK5";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
			};

			buck6: BUCK6 {
				regulator-name = "BUCK6";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
			};

			ldo1: LDO1 {
				regulator-name = "LDO1";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
			};

			ldo4: LDO4 {
				regulator-name = "LDO4";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
			};

			ldo5: LDO5 {
				regulator-name = "LDO5";
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	eeprom: eeprom@50 {
		compatible = "atmel,24c256";
		reg = <0x50>;
		pagesize = <64>;
	};
};

&lpi2c3 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <400000>;
	pinctrl-0 = <&pinctrl_lpi2c3>;
	pinctrl-names = "default";
	status = "okay";

	ptn5110: tcpc@50 {
		compatible = "nxp,ptn5110", "tcpci";
		reg = <0x50>;
		interrupt-parent = <&gpio3>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;

		typec1_con: connector {
			compatible = "usb-c-connector";
			data-role = "dual";
			label = "USB-C";
			op-sink-microwatt = <15000000>;
			power-role = "dual";
			self-powered;
			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
				     PDO_VAR(5000, 20000, 3000)>;
			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
			try-power-role = "sink";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					typec1_dr_sw: endpoint {
						remote-endpoint = <&usb1_drd_sw>;
					};
				};
			};
		};
	};

	pcf2131: rtc@53 {
		compatible = "nxp,pcf2131";
		reg = <0x53>;
		interrupt-parent = <&pcal6524>;
		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
	};
};

&lpuart1 { /* console */
	pinctrl-0 = <&pinctrl_uart1>;
	pinctrl-names = "default";
	status = "okay";
};

&usbotg1 {
	adp-disable;
	disable-over-current;
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	usb-role-switch;
	samsung,picophy-dc-vol-level-adjust = <7>;
	samsung,picophy-pre-emp-curr-control = <3>;
	status = "okay";

	port {

		usb1_drd_sw: endpoint {
			remote-endpoint = <&typec1_dr_sw>;
		};
	};
};

&usbotg2 {
	disable-over-current;
	dr_mode = "host";
	samsung,picophy-dc-vol-level-adjust = <7>;
	samsung,picophy-pre-emp-curr-control = <3>;
	status = "okay";
};

&usdhc1 {
	bus-width = <8>;
	non-removable;
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	status = "okay";
};

&usdhc2 {
	bus-width = <4>;
	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
	no-mmc;
	no-sdio;
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&wdog3 {
	status = "okay";
};

&iomuxc {

	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e
			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x58e
			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e
			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e
			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
		>;
	};

	pinctrl_eqos_sleep: eqossleepgrp {
		fsl,pins = <
			MX93_PAD_ENET1_MDC__GPIO4_IO00				0x31e
			MX93_PAD_ENET1_MDIO__GPIO4_IO01				0x31e
			MX93_PAD_ENET1_RD0__GPIO4_IO10                          0x31e
			MX93_PAD_ENET1_RD1__GPIO4_IO11				0x31e
			MX93_PAD_ENET1_RD2__GPIO4_IO12				0x31e
			MX93_PAD_ENET1_RD3__GPIO4_IO13				0x31e
			MX93_PAD_ENET1_RXC__GPIO4_IO09                          0x31e
			MX93_PAD_ENET1_RX_CTL__GPIO4_IO08			0x31e
			MX93_PAD_ENET1_TD0__GPIO4_IO05                          0x31e
			MX93_PAD_ENET1_TD1__GPIO4_IO04                          0x31e
			MX93_PAD_ENET1_TD2__GPIO4_IO03				0x31e
			MX93_PAD_ENET1_TD3__GPIO4_IO02				0x31e
			MX93_PAD_ENET1_TXC__GPIO4_IO07                          0x31e
			MX93_PAD_ENET1_TX_CTL__GPIO4_IO06                       0x31e
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e
			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e
			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x58e
			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e
			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e
			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e
			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e
			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e
			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e
		>;
	};

	pinctrl_fec_sleep: fecsleepgrp {
		fsl,pins = <
			MX93_PAD_ENET2_MDC__GPIO4_IO14			0x51e
			MX93_PAD_ENET2_MDIO__GPIO4_IO15			0x51e
			MX93_PAD_ENET2_RD0__GPIO4_IO24			0x51e
			MX93_PAD_ENET2_RD1__GPIO4_IO25			0x51e
			MX93_PAD_ENET2_RD2__GPIO4_IO26			0x51e
			MX93_PAD_ENET2_RD3__GPIO4_IO27			0x51e
			MX93_PAD_ENET2_RXC__GPIO4_IO23                  0x51e
			MX93_PAD_ENET2_RX_CTL__GPIO4_IO22		0x51e
			MX93_PAD_ENET2_TD0__GPIO4_IO19			0x51e
			MX93_PAD_ENET2_TD1__GPIO4_IO18			0x51e
			MX93_PAD_ENET2_TD2__GPIO4_IO17			0x51e
			MX93_PAD_ENET2_TD3__GPIO4_IO16			0x51e
			MX93_PAD_ENET2_TXC__GPIO4_IO21                  0x51e
			MX93_PAD_ENET2_TX_CTL__GPIO4_IO20               0x51e
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX93_PAD_GPIO_IO25__CAN2_TX	0x139e
			MX93_PAD_GPIO_IO27__CAN2_RX	0x139e
		>;
	};

	pinctrl_lpi2c2: lpi2c2grp {
		fsl,pins = <
			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
		>;
	};

	pinctrl_lpi2c3: lpi2c3grp {
		fsl,pins = <
			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e
			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e
		>;
	};

	pinctrl_pcal6524: pcal6524grp {
		fsl,pins = <
			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e
			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX93_PAD_SD1_CLK__USDHC1_CLK		0x1582
			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001382
			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x40001382
			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001382
			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x40001382
			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001382
			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001382
			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001382
			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001382
			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001382
			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1582
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX93_PAD_SD1_CLK__USDHC1_CLK		0x158e
			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000138e
			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000138e
			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e
			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000138e
			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000138e
			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000138e
			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000138e
			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000138e
			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x158e
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe
			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400013fe
			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x400013fe
			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013fe
			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013fe
			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013fe
			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013fe
			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013fe
			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013fe
			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013fe
			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
		>;
	};

	pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
		fsl,pins = <
			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x51e
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX93_PAD_SD2_CLK__USDHC2_CLK		0x1582
			MX93_PAD_SD2_CMD__USDHC2_CMD		0x40001382
			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x40001382
			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x40001382
			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x40001382
			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x40001382
			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e
			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000138e
			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e
			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e
			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e
			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000138e
			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX93_PAD_SD2_CLK__USDHC2_CLK		0x15fe
			MX93_PAD_SD2_CMD__USDHC2_CMD		0x400013fe
			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x400013fe
			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x400013fe
			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x400013fe
			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x400013fe
			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
		>;
	};

	pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
		fsl,pins = <
			MX93_PAD_SD2_CLK__GPIO3_IO01            0x51e
			MX93_PAD_SD2_CMD__GPIO3_IO02		0x51e
			MX93_PAD_SD2_DATA0__GPIO3_IO03		0x51e
			MX93_PAD_SD2_DATA1__GPIO3_IO04		0x51e
			MX93_PAD_SD2_DATA2__GPIO3_IO05		0x51e
			MX93_PAD_SD2_DATA3__GPIO3_IO06		0x51e
			MX93_PAD_SD2_VSELECT__GPIO3_IO19	0x51e
		>;
	};
};
